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x1000: restore crt0.S cache flush

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I-cache must be flushed after copying code to IRAM... duh.

Change-Id: I6eacc4b7c4385175724c947f6c53f7bbddcb6295
This commit is contained in:
Aidan MacDonald 2022-03-16 19:25:51 +00:00
parent c676736792
commit 67f7d399e5
1 changed files with 19 additions and 1 deletions
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20
firmware/target/mips/ingenic_x1000/crt0.S
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@ -7,7 +7,7 @@
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2021 Aidan MacDonald
* Copyright (C) 2021-2022 Aidan MacDonald
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -82,6 +82,24 @@ _realstart:
bal _clear
move a1, k0
/* Write back D-cache and invalidate I-cache */
li v0, 0x80000000
ori v1, v0, (0x4000 - 32)
mtc0 zero, C0_TAGLO
mtc0 zero, C0_TAGHI
1:
cache DCIndexWBInv, 0(v0)
cache ICIndexStTag, 0(v0)
bne v0, v1, 1b
addiu v0, v0, 32
/* Invalidate BTB */
mfc0 v0, C0_Config, 7
nop
ori v0, v0, 2
mtc0 v0, C0_Config, 7
nop
/* Jump to C code */
jal system_early_init
nop