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add cpu frequency scaling to the gigabeat. default/normal: 100MHz, boosted: 300MHz

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12023 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Marcoen Hirschberg 2007-01-16 15:49:29 +00:00
parent 0fedaa205c
commit 6309eabc64
3 changed files with 33 additions and 2 deletions
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3
firmware/export/config-gigabeat.h
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@ -124,10 +124,9 @@
#define USB_GIGABEAT_STYLE #define USB_GIGABEAT_STYLE
#define HAVE_HEADPHONE_DETECTION #define HAVE_HEADPHONE_DETECTION
/* Define this if you have adjustable CPU frequency */ /* Define this if you have adjustable CPU frequency */
#if 0 /* TODO */
#define HAVE_ADJUSTABLE_CPU_FREQ #define HAVE_ADJUSTABLE_CPU_FREQ
#endif
#define BOOTFILE_EXT "gigabeat" #define BOOTFILE_EXT "gigabeat"
#define BOOTFILE "rockbox." BOOTFILE_EXT #define BOOTFILE "rockbox." BOOTFILE_EXT

10
firmware/export/system.h
View file

@ -273,6 +273,14 @@ static inline unsigned long swap32(unsigned long value)
/* TODO: Implement set_irq_level and check CPU frequencies */ /* TODO: Implement set_irq_level and check CPU frequencies */
#if CONFIG_CPU == S3C2440
#define CPUFREQ_DEFAULT 98784000
#define CPUFREQ_NORMAL 98784000
#define CPUFREQ_MAX 296352000
#else
#define CPUFREQ_DEFAULT_MULT 8 #define CPUFREQ_DEFAULT_MULT 8
#define CPUFREQ_DEFAULT 24000000 #define CPUFREQ_DEFAULT 24000000
#define CPUFREQ_NORMAL_MULT 10 #define CPUFREQ_NORMAL_MULT 10
@ -280,6 +288,8 @@ static inline unsigned long swap32(unsigned long value)
#define CPUFREQ_MAX_MULT 25 #define CPUFREQ_MAX_MULT 25
#define CPUFREQ_MAX 75000000 #define CPUFREQ_MAX 75000000
#endif
static inline unsigned short swap16(unsigned short value) static inline unsigned short swap16(unsigned short value)
/* /*
result[15..8] = value[ 7..0]; result[15..8] = value[ 7..0];

22
firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c
View file

@ -68,4 +68,26 @@ void system_init(void)
} }
void set_cpu_frequency(long frequency)
{
if (frequency == CPUFREQ_MAX)
{
/* FCLK: 300MHz, HCLK: 100MHz, PCLK: 50MHz */
/* MDIV: 97, PDIV: 1, SDIV: 2 */
/* HDIV: 3, PDIV: 1 */
MPLLCON = (97 << 12) | (1 << 4) | 2;
CLKDIVN = (3 << 1) | 1;
FREQ = CPUFREQ_MAX;
}
else
{
/* FCLK: 200MHz, HCLK: 100MHz, PCLK: 50MHz */
/* MDIV: 62, PDIV: 1, SDIV: 2 */
/* HDIV: 1, PDIV: 1 */
MPLLCON = (62 << 12) | (1 << 4) | 3;
CLKDIVN = (0 << 1) | 1;
FREQ = CPUFREQ_NORMAL;
}
}