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Ondio: (Hopefully) fix the occasional freezes during playback: Use DMA channel 0 for MMC transfer. As it has higher priority than channel 3 (used for playback), the risk of serial receive overruns is minimised.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9885 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2006-05-07 20:20:27 +00:00
parent 595a204020
commit 61b8604a9c
1 changed files with 14 additions and 14 deletions
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28
firmware/drivers/ata_mmc.c
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@ -583,12 +583,12 @@ static int receive_block(unsigned char *inbuf, int size, long timeout)
SCR1 = 0; /* disable serial */ SCR1 = 0; /* disable serial */
SSR1 = 0; /* clear all flags */ SSR1 = 0; /* clear all flags */
/* setup DMA channel 2 */ /* setup DMA channel 0 */
CHCR2 = 0; /* disable */ CHCR0 = 0; /* disable */
SAR2 = RDR1_ADDR; SAR0 = RDR1_ADDR;
DAR2 = (unsigned long) inbuf; DAR0 = (unsigned long) inbuf;
DTCR2 = size; DTCR0 = size;
CHCR2 = 0x4601; /* fixed source address, RXI1, enable */ CHCR0 = 0x4601; /* fixed source address, RXI1, enable */
DMAOR = 0x0001; DMAOR = 0x0001;
SCR1 = (SCI_RE|SCI_RIE); /* kick off DMA */ SCR1 = (SCI_RE|SCI_RIE); /* kick off DMA */
@ -600,7 +600,7 @@ static int receive_block(unsigned char *inbuf, int size, long timeout)
bg_copy_swap(); bg_copy_swap();
yield(); /* be nice */ yield(); /* be nice */
while (!(CHCR2 & 0x0002)); /* wait for end of DMA */ while (!(CHCR0 & 0x0002)); /* wait for end of DMA */
while (!(SSR1 & SCI_ORER)); /* wait for the trailing bytes */ while (!(SSR1 & SCI_ORER)); /* wait for the trailing bytes */
SCR1 = 0; SCR1 = 0;
serial_mode = SER_DISABLED; serial_mode = SER_DISABLED;
@ -625,19 +625,19 @@ static int send_block(int size, unsigned char start_token, long timeout)
SCR1 = 0; /* disable serial */ SCR1 = 0; /* disable serial */
SSR1 = 0; /* clear all flags */ SSR1 = 0; /* clear all flags */
/* setup DMA channel 2 */ /* setup DMA channel 0 */
CHCR2 = 0; /* disable */ CHCR0 = 0; /* disable */
SAR2 = (unsigned long)(curbuf + 1); SAR0 = (unsigned long)(curbuf + 1);
DAR2 = TDR1_ADDR; DAR0 = TDR1_ADDR;
DTCR2 = size + 3; /* start token + block + dummy crc */ DTCR0 = size + 3; /* start token + block + dummy crc */
CHCR2 = 0x1701; /* fixed dest. address, TXI1, enable */ CHCR0 = 0x1701; /* fixed dest. address, TXI1, enable */
DMAOR = 0x0001; DMAOR = 0x0001;
SCR1 = (SCI_TE|SCI_TIE); /* kick off DMA */ SCR1 = (SCI_TE|SCI_TIE); /* kick off DMA */
bg_copy_swap(); bg_copy_swap();
yield(); /* be nice */ yield(); /* be nice */
while (!(CHCR2 & 0x0002)); /* wait for end of DMA */ while (!(CHCR0 & 0x0002)); /* wait for end of DMA */
while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */ while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
SCR1 = 0; SCR1 = 0;
serial_mode = SER_DISABLED; serial_mode = SER_DISABLED;