forked from len0rd/rockbox
iPod 1st..3rd gen: Fix CPU scaling instability on PP5002 * Add some new info to pp5002.h and sort it by port address.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14053 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
62c8e2d69d
commit
604e44d0e2
3 changed files with 94 additions and 89 deletions
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@ -1278,7 +1278,7 @@ bool dbg_ports(void)
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lcd_puts(0, line++, buf);
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snprintf(buf, sizeof(buf), "CLOCK_SOURCE: %08lx", CLOCK_SOURCE);
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lcd_puts(0, line++, buf);
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snprintf(buf, sizeof(buf), "CLOCK_DIV: %08lx", CLOCK_DIV);
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snprintf(buf, sizeof(buf), "PLL_CONTROL: %08lx", PLL_CONTROL);
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lcd_puts(0, line++, buf);
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snprintf(buf, sizeof(buf), "PLL_DIV: %08lx", PLL_DIV);
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lcd_puts(0, line++, buf);
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@ -19,13 +19,24 @@
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#ifndef __PP5002_H__
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#define __PP5002_H__
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/* All info gleaned and/or copied from the iPodLinux project. */
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/* Much info gleaned and/or copied from the iPodLinux project. */
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#define DRAM_START 0x28000000
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#define IPOD_LCD_BASE 0xc0001000
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#define CPU_CTL (*(volatile unsigned char *)(0xcf004054))
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#define COP_CTL (*(volatile unsigned char *)(0xcf004058))
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#define IISCONFIG (*(volatile unsigned long *)(0xc0002500))
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#define IISFIFO_CFG (*(volatile unsigned long *)(0xc000251c))
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#define IISFIFO_WR (*(volatile unsigned long *)(0xc0002540))
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#define IISFIFO_RD (*(volatile unsigned long *)(0xc0002580))
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#define I2C_BASE 0xc0008000
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/* The PortalPlayer USB controller uses base address 0xc5000000 */
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#define USB_BASE 0xc5000000
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#define USB2D_IDENT (*(volatile unsigned long *)(0xc5000000))
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#define USB_STATUS (*(volatile unsigned long *)(0xc50001a4))
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#define GPIOA_ENABLE (*(volatile unsigned char *)(0xcf000000))
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#define GPIOB_ENABLE (*(volatile unsigned char *)(0xcf000004))
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@ -60,84 +71,78 @@
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#define GPIOC_INT_CLR (*(volatile unsigned char *)(0xcf000078))
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#define GPIOD_INT_CLR (*(volatile unsigned char *)(0xcf00007c))
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#define DEV_RS (*(volatile unsigned long *)( 0xcf005030))
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#define DEV_EN (*(volatile unsigned long *)( 0xcf005000))
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#define DEV_I2C (1<<8)
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#define DEV_USB 0x400000
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#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
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#define INIT_USB 0x80000000
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#define CPU_INT_STAT (*(volatile unsigned long*)(0xcf001000))
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#define CPU_INT_EN (*(volatile unsigned long*)(0xcf001024))
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#define CPU_INT_CLR (*(volatile unsigned long*)(0xcf001028))
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#define COP_INT_STAT (*(volatile unsigned long*)(0xcf001010)) /* A guess */
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#define COP_INT_EN (*(volatile unsigned long*)(0xcf001034))
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#define COP_INT_CLR (*(volatile unsigned long*)(0xcf001038))
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#define USB2D_IDENT (*(volatile unsigned long*)(0xc5000000))
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#define USB_STATUS (*(volatile unsigned long*)(0xc50001a4))
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#define IISCONFIG (*(volatile unsigned long*)(0xc0002500))
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#define IISFIFO_CFG (*(volatile unsigned long*)(0xc000251c))
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#define IISFIFO_WR (*(volatile unsigned long*)(0xc0002540))
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#define IISFIFO_RD (*(volatile unsigned long*)(0xc0002580))
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#define I2C_BASE 0xc0008000
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#define TIMER1_CFG (*(volatile unsigned long *)(0xcf001100))
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#define TIMER1_VAL (*(volatile unsigned long *)(0xcf001104))
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#define TIMER2_CFG (*(volatile unsigned long *)(0xcf001108))
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#define TIMER2_VAL (*(volatile unsigned long *)(0xcf00110c))
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#define USEC_TIMER (*(volatile unsigned long *)(0xcf001110))
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#define PP5002_TIMER_STATUS 0xcf001110
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#define INT_FORCED_CLR (*(volatile unsigned long *)(0xcf00101c))
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#define CPU_INT_STAT (*(volatile unsigned long *)(0xcf001000))
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#define CPU_INT_EN (*(volatile unsigned long *)(0xcf001024))
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#define CPU_INT_CLR (*(volatile unsigned long *)(0xcf001028))
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#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
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#define COP_INT_STAT (*(volatile unsigned long *)(0xcf001010))
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#define COP_INT_EN (*(volatile unsigned long *)(0xcf001034))
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#define COP_INT_CLR (*(volatile unsigned long *)(0xcf001038))
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#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
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#define IDE_IRQ 1
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#define SER0_IRQ 4
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#define I2S_IRQ 5
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#define SER1_IRQ 7
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#define TIMER1_IRQ 11
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#define TIMER2_IRQ 12 /* NOTE: THIS IS A GUESS, NEEDS TESTING */
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#define TIMER2_IRQ 12
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#define GPIO_IRQ 14
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#define DMA_OUT_IRQ 30
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#define DMA_IN_IRQ 31
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#define TIMER1_MASK (1 << TIMER1_IRQ)
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#define TIMER2_MASK (1 << TIMER2_IRQ)
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#define I2S_MASK (1 << I2S_IRQ)
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#define IDE_MASK (1 << IDE_IRQ)
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#define GPIO_MASK (1 << GPIO_IRQ)
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#define SER0_MASK (1 << SER0_IRQ)
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#define SER1_MASK (1 << SER1_IRQ)
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#define DMA_OUT_MASK (1 << DMA_OUT_IRQ)
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#define IDE_MASK (1 << IDE_IRQ)
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#define SER0_MASK (1 << SER0_IRQ)
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#define I2S_MASK (1 << I2S_IRQ)
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#define SER1_MASK (1 << SER1_IRQ)
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#define TIMER1_MASK (1 << TIMER1_IRQ)
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#define TIMER2_MASK (1 << TIMER2_IRQ)
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#define GPIO_MASK (1 << GPIO_IRQ)
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#define DMA_OUT_MASK (1 << DMA_OUT_IRQ)
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#define DMA_IN_MASK (1 << DMA_IN_IRQ)
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#define TIMING1_CTL (*(volatile unsigned long*)(0xcf004000))
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#define TIMING2_CTL (*(volatile unsigned long*)(0xcf004008))
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#define CLOCK_ENABLE (*(volatile unsigned long*)(0xcf005008))
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#define CLOCK_SOURCE (*(volatile unsigned long*)(0xcf00500c))
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#define CLOCK_DIV (*(volatile unsigned long*)(0xcf005010))
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#define PLL_DIV (*(volatile unsigned long*)(0xcf005018))
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#define PLL_MULT (*(volatile unsigned long*)(0xcf00501c))
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#define TIMER1_CFG (*(volatile unsigned long *)(0xcf001100))
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#define TIMER1_VAL (*(volatile unsigned long *)(0xcf001104))
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#define TIMER2_CFG (*(volatile unsigned long *)(0xcf001108))
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#define TIMER2_VAL (*(volatile unsigned long *)(0xcf00110c))
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#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
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#define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c))
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#define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010))
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#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
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#define USEC_TIMER (*(volatile unsigned long *)(0xcf001110))
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/* The PortalPlayer USB controller uses base address 0xc5000000 */
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#define USB_BASE 0xc5000000
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#define TIMING1_CTL (*(volatile unsigned long *)(0xcf004000))
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#define TIMING2_CTL (*(volatile unsigned long *)(0xcf004008))
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#define PROC_SLEEP 0xca
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#define PROC_WAKE 0xce
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#define CPU_CTL (*(volatile unsigned char *)(0xcf004054))
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#define COP_CTL (*(volatile unsigned char *)(0xcf004058))
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#define PROC_SLEEP 0xca
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#define PROC_WAKE 0xce
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#define DEV_EN (*(volatile unsigned long *)(0xcf005000))
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#define DEV_RS (*(volatile unsigned long *)(0xcf005030))
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#define DEV_I2C (1<<8)
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#define DEV_USB 0x400000
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#define CLOCK_ENABLE (*(volatile unsigned long *)(0xcf005008))
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#define CLOCK_SOURCE (*(volatile unsigned long *)(0xcf00500c))
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#define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010))
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#define PLL_DIV (*(volatile unsigned long *)(0xcf005018))
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#define PLL_MULT (*(volatile unsigned long *)(0xcf00501c))
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#define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long *)(0xf000f008))
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#define MMAP1_PHYSICAL (*(volatile unsigned long *)(0xf000f00c))
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#define MMAP2_LOGICAL (*(volatile unsigned long *)(0xf000f010))
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#define MMAP2_PHYSICAL (*(volatile unsigned long *)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long *)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long *)(0xf000f01c))
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/* FIXME: These are PP502x definitions, but without them, iPod 3rd gen
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* doesn't compile. The correct values for 3rd gen are not yet known. */
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#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
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#define INIT_USB 0x80000000
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#endif
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@ -96,40 +96,34 @@ void set_cpu_frequency(long frequency)
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cpu_frequency = frequency;
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outl(0xd19b, 0xcf005038);
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outl(0x02, 0xcf005008);
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outl(0x55, 0xcf00500c);
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outl(0x6000, 0xcf005010);
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outl(inl(0xcf005010) | 0x6000, 0xcf005010);
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outl(0x01, 0xcf005008);
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outl(0xa9, 0xcf00500c);
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outl(0xe000, 0xcf005010);
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/* Clock frequency = (24/4)*postmult */
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outl(4, 0xcf005018);
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outl(postmult, 0xcf00501c);
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outl(0xe000, 0xcf005010);
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/* Wait for PLL relock? */
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udelay(2000);
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udelay(200);
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/* Select PLL as clock source? */
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outl(0xa8, 0xcf00500c);
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outl(0x02, 0xcf005008);
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}
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}
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#elif !defined(BOOTLOADER)
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static void ipod_set_cpu_speed(void)
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{
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outl(0xd19b, 0xcf005038);
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outl(0x02, 0xcf005008);
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outl(0x55, 0xcf00500c);
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outl(0x6000, 0xcf005010);
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#if 1
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// 75 MHz (24/24 * 75) (default)
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outl(24, 0xcf005018);
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outl(75, 0xcf00501c);
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#endif
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#if 0
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// 66 MHz (24/3 * 8)
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outl(3, 0xcf005018);
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outl(8, 0xcf00501c);
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#endif
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/* 78 MHz (24*13/4) */
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outl(4, 0xcf005018);
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outl(13, 0xcf00501c);
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outl(0xe000, 0xcf005010);
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@ -148,9 +142,15 @@ void system_init(void)
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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outl(-1, 0xcf00101c);
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outl(-1, 0xcf001028);
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outl(-1, 0xcf001038);
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INT_FORCED_CLR = -1;
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CPU_INT_CLR = -1;
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COP_INT_CLR = -1;
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GPIOA_INT_EN = 0;
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GPIOB_INT_EN = 0;
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GPIOC_INT_EN = 0;
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GPIOD_INT_EN = 0;
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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ipod_set_cpu_speed();
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#endif
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