devs/foxbox
1
0
Fork 0
forked from len0rd/rockbox
Code Pull requests Activity

Gigabeat S: Man it's so loud in here. We have SOUND! Someone please make keymaps consistent; it's rather messy atm.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17327 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-05-03 15:14:52 +00:00
parent d0e32119f1
commit 5df4405317
9 changed files with 1503 additions and 496 deletions
Download patch file Download diff file Expand all files Collapse all files

309
firmware/drivers/audio/wm8978.c
View file

@ -23,9 +23,20 @@
#include "audiohw.h"
#include "wmcodec.h"
#include "audio.h"
//#define LOGF_ENABLE
#include "logf.h"
const struct sound_settings_info audiohw_settings[] = {
[SOUND_VOLUME] = {"dB", 0, 1, -58, 6, -25},
#define HW_VOL_MIN 0
#define HW_VOL_MUTE 0
#define HW_VOL_MAX 96
/* TODO: Define/refine an API for special hardware steps outside the
* main codec driver such as special GPIO handling. */
extern void audiohw_enable_headphone_jack(bool enable);
const struct sound_settings_info audiohw_settings[] =
{
[SOUND_VOLUME] = {"dB", 0, 1, -90, 6, -25},
[SOUND_BASS] = {"dB", 0, 1, -12, 12, 0},
[SOUND_TREBLE] = {"dB", 0, 1, -12, 12, 0},
[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
@ -33,28 +44,318 @@ const struct sound_settings_info audiohw_settings[] = {
[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
[SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0},
[SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0},
#if 0
[SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16},
#endif
#if 0
[SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 1},
[SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
#endif
};
static uint16_t wmc_regs[WMC_NUM_REGISTERS] =
{
/* Initialized with post-reset default values - the 2-wire interface
* cannot be read. Or-in additional bits desired for some registers. */
[0 ... WMC_NUM_REGISTERS-1] = 0x8000, /* To ID invalids in gaps */
[WMC_SOFTWARE_RESET] = 0x000,
[WMC_POWER_MANAGEMENT1] = 0x000,
[WMC_POWER_MANAGEMENT2] = 0x000,
[WMC_POWER_MANAGEMENT3] = 0x000,
[WMC_AUDIO_INTERFACE] = 0x050,
[WMC_COMPANDING_CTRL] = 0x000,
[WMC_CLOCK_GEN_CTRL] = 0x140,
[WMC_ADDITIONAL_CTRL] = 0x000,
[WMC_GPIO] = 0x000,
[WMC_JACK_DETECT_CONTROL1] = 0x000,
[WMC_DAC_CONTROL] = 0x000,
[WMC_LEFT_DAC_DIGITAL_VOL] = 0x0ff | WMC_VU,
[WMC_RIGHT_DAC_DIGITAL_VOL] = 0x0ff | WMC_VU,
[WMC_JACK_DETECT_CONTROL2] = 0x000,
[WMC_ADC_CONTROL] = 0x100,
[WMC_LEFT_ADC_DIGITAL_VOL] = 0x0ff | WMC_VU,
[WMC_RIGHT_ADC_DIGITAL_VOL] = 0x0ff | WMC_VU,
[WMC_EQ1_LOW_SHELF] = 0x12c,
[WMC_EQ2_PEAK1] = 0x02c,
[WMC_EQ3_PEAK2] = 0x02c,
[WMC_EQ4_PEAK3] = 0x02c,
[WMC_EQ5_HIGH_SHELF] = 0x02c,
[WMC_DAC_LIMITER1] = 0x032,
[WMC_DAC_LIMITER2] = 0x000,
[WMC_NOTCH_FILTER1] = 0x000,
[WMC_NOTCH_FILTER2] = 0x000,
[WMC_NOTCH_FILTER3] = 0x000,
[WMC_NOTCH_FILTER4] = 0x000,
[WMC_ALC_CONTROL1] = 0x038,
[WMC_ALC_CONTROL2] = 0x00b,
[WMC_ALC_CONTROL3] = 0x032,
[WMC_NOISE_GATE] = 0x000,
[WMC_PLL_N] = 0x008,
[WMC_PLL_K1] = 0x00c,
[WMC_PLL_K2] = 0x093,
[WMC_PLL_K3] = 0x0e9,
[WMC_3D_CONTROL] = 0x000,
[WMC_BEEP_CONTROL] = 0x000,
[WMC_INPUT_CTRL] = 0x033,
[WMC_LEFT_INP_PGA_GAIN_CTRL] = 0x010,
[WMC_RIGHT_INP_PGA_GAIN_CTRL] = 0x010,
[WMC_LEFT_ADC_BOOST_CTRL] = 0x100,
[WMC_RIGHT_ADC_BOOST_CTRL] = 0x100,
[WMC_OUTPUT_CTRL] = 0x002,
[WMC_LEFT_MIXER_CTRL] = 0x001,
[WMC_RIGHT_MIXER_CTRL] = 0x001,
[WMC_LOUT1_HP_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
[WMC_ROUT1_HP_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
[WMC_LOUT2_SPK_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
[WMC_ROUT2_SPK_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
[WMC_OUT3_MIXER_CTRL] = 0x001,
[WMC_OUT4_MONO_MIXER_CTRL] = 0x001,
};
struct
{
int vol_l;
int vol_r;
bool ahw_mute;
} wmc_vol =
{
0, 0, false
};
static void wmc_write(unsigned int reg, unsigned int val)
{
if (reg >= WMC_NUM_REGISTERS || (wmc_regs[reg] & 0x8000))
{
logf("wm8978 invalid register: %d", reg);
return;
}
wmc_regs[reg] = val & ~0x8000;
wmcodec_write(reg, val);
}
static void wmc_set(unsigned int reg, unsigned int bits)
{
wmc_write(reg, wmc_regs[reg] | bits);
}
static void wmc_clear(unsigned int reg, unsigned int bits)
{
wmc_write(reg, wmc_regs[reg] & ~bits);
}
static void wmc_write_masked(unsigned int reg, unsigned int bits,
unsigned int mask)
{
wmc_write(reg, (wmc_regs[reg] & ~mask) | (bits & mask));
}
/* convert tenth of dB volume (-890..60) to master volume register value
* (000000...111111) */
int tenthdb2master(int db)
{
/* -90dB to +6dB 1dB steps (96 levels) 7bits */
/* 1100000 == +6dB (0x60,96) */
/* 1101010 == 0dB (0x5a,90) */
/* 1000001 == -57dB (0x21,33,DAC) */
/* 0000001 == -89dB (0x01,01) */
/* 0000000 == -90dB (0x00,00,Mute) */
if (db <= VOLUME_MIN)
{
return 0x0;
}
else
{
return (db - VOLUME_MIN) / 10;
}
}
void audiohw_preinit(void)
{
wmcodec_write(WM8978_SOFTWARE_RESET, 0);
/* 1. Turn on external power supplies. Wait for supply voltage to settle. */
/* Step 1 should be completed already. Reset and return all registers to
* defaults */
wmcodec_write(WMC_SOFTWARE_RESET, 0xff);
sleep(HZ/10);
/* 2. Mute all analogue outputs */
wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
wmc_set(WMC_LOUT2_SPK_VOLUME_CTRL, WMC_MUTE);
wmc_set(WMC_ROUT2_SPK_VOLUME_CTRL, WMC_MUTE);
wmc_set(WMC_OUT3_MIXER_CTRL, WMC_MUTE);
wmc_set(WMC_OUT4_MONO_MIXER_CTRL, WMC_MUTE);
wmc_set(WMC_INPUT_CTRL, 0x000);
/* 3. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3. */
wmc_write(WMC_POWER_MANAGEMENT3,
WMC_RMIXEN | WMC_LMIXEN | WMC_DACENR | WMC_DACENL);
/* 4. Set BUFIOEN = 1 and VMIDSEL[1:0] to required value in register
* R1. Wait for VMID supply to settle */
wmc_write(WMC_POWER_MANAGEMENT1, WMC_BUFIOEN | WMC_VMIDSEL_300K);
sleep(HZ/10);
/* 5. Set BIASEN = 1 in register R1. */
wmc_set(WMC_POWER_MANAGEMENT1, WMC_BIASEN);
}
void audiohw_postinit(void)
{
sleep(HZ);
/* 6. Set L/ROUTEN = 1 in register R2. */
wmc_write(WMC_POWER_MANAGEMENT2, WMC_LOUT1EN | WMC_ROUT1EN);
/* 7. Enable other mixers as required */
/* 8. Enable other outputs as required */
/* 9. Set remaining registers */
wmc_write(WMC_AUDIO_INTERFACE, WMC_WL_16 | WMC_FMT_I2S
| WMC_DACLRSWAP | WMC_ADCLRSWAP);
wmc_write(WMC_DAC_CONTROL, WMC_DACOSR_128 | WMC_AMUTE);
/* Specific to HW clocking */
wmc_write(WMC_CLOCK_GEN_CTRL, WMC_MCLKDIV_1_5 | WMC_BCLKDIV_8 | WMC_MS);
wmc_write(WMC_ADDITIONAL_CTRL, WMC_SR_48KHZ); /* 44.1 */
/* Initialize to minimum volume */
wmc_write_masked(WMC_LEFT_DAC_DIGITAL_VOL, 189, WMC_DVOL);
wmc_write_masked(WMC_LOUT1_HP_VOLUME_CTRL, 0, WMC_AVOL);
wmc_write_masked(WMC_RIGHT_DAC_DIGITAL_VOL, 189, WMC_DVOL);
wmc_write_masked(WMC_ROUT1_HP_VOLUME_CTRL, 0, WMC_AVOL);
/* ADC silenced */
wmc_write_masked(WMC_LEFT_ADC_DIGITAL_VOL, 0x00, WMC_DVOL);
wmc_write_masked(WMC_RIGHT_ADC_DIGITAL_VOL, 0x00, WMC_DVOL);
audiohw_enable_headphone_jack(true);
}
void audiohw_set_headphone_vol(int vol_l, int vol_r)
{
int prev_l = wmc_vol.vol_l;
int prev_r = wmc_vol.vol_r;
int dac_l, dac_r;
wmc_vol.vol_l = vol_l;
wmc_vol.vol_r = vol_r;
/* When analogue volume falls below -57dB (0x00) start attenuating the
* DAC volume */
if (vol_l >= 33)
{
if (vol_l > HW_VOL_MAX)
vol_l = HW_VOL_MAX;
dac_l = 255;
vol_l -= 33;
}
else
{
if (vol_l < HW_VOL_MIN)
vol_l = HW_VOL_MIN;
dac_l = 2*vol_l + 189;
vol_l = 0;
}
if (vol_r >= 33)
{
if (vol_r > HW_VOL_MAX)
vol_r = HW_VOL_MAX;
dac_r = 255;
vol_r -= 33;
}
else
{
if (vol_r < HW_VOL_MIN)
vol_r = HW_VOL_MIN;
dac_r = 2*vol_r + 189;
vol_r = 0;
}
/* Have to write both channels always to have the latching work */
wmc_write_masked(WMC_LEFT_DAC_DIGITAL_VOL, dac_l, WMC_DVOL);
wmc_write_masked(WMC_LOUT1_HP_VOLUME_CTRL, vol_l, WMC_AVOL);
wmc_write_masked(WMC_RIGHT_DAC_DIGITAL_VOL, dac_r, WMC_DVOL);
wmc_write_masked(WMC_ROUT1_HP_VOLUME_CTRL, vol_r, WMC_AVOL);
if (wmc_vol.vol_l > HW_VOL_MUTE)
{
/* Not muted and going up from mute level? */
if (prev_l <= HW_VOL_MUTE && !wmc_vol.ahw_mute)
wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
}
else
{
/* Going to mute level? */
if (prev_l > HW_VOL_MUTE)
wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
}
if (wmc_vol.vol_r > HW_VOL_MUTE)
{
/* Not muted and going up from mute level? */
if (prev_r <= HW_VOL_MIN && !wmc_vol.ahw_mute)
wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
}
else
{
/* Going to mute level? */
if (prev_r > HW_VOL_MUTE)
wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
}
}
void audiohw_close(void)
{
/* 1. Mute all analogue outputs */
audiohw_mute(true);
audiohw_enable_headphone_jack(false);
/* 2. Disable power management register 1. R1 = 00 */
wmc_write(WMC_POWER_MANAGEMENT1, 0x000);
/* 3. Disable power management register 2. R2 = 00 */
wmc_write(WMC_POWER_MANAGEMENT2, 0x000);
/* 4. Disable power management register 3. R3 = 00 */
wmc_write(WMC_POWER_MANAGEMENT3, 0x000);
/* 5. Remove external power supplies. */
}
void audiohw_mute(bool mute)
{
(void)mute;
wmc_vol.ahw_mute = mute;
/* No DAC mute here, please - take care of each enabled output. */
if (mute)
{
wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
}
else
{
/* Unmute outputs not at mute level */
if (wmc_vol.vol_l > HW_VOL_MUTE)
wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
if (wmc_vol.vol_r > HW_VOL_MUTE)
wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
}
}
#ifdef HAVE_RECORDING
/* TODO */
void audiohw_set_recvol(int left, int right, int type)
{
(void)left; (void)right; (void)type;
}
#endif

407
firmware/export/imx31l.h
View file

@ -717,6 +717,296 @@
/* I2DR - [7:0] Data */
/* AUDMUX */
#define AUDMUX_PTCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x00))
#define AUDMUX_PDCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x04))
#define AUDMUX_PTCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x08))
#define AUDMUX_PDCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x0C))
#define AUDMUX_PTCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x10))
#define AUDMUX_PDCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x14))
#define AUDMUX_PTCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x18))
#define AUDMUX_PDCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x1C))
#define AUDMUX_PTCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x20))
#define AUDMUX_PDCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x24))
#define AUDMUX_PTCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x28))
#define AUDMUX_PDCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x2C))
#define AUDMUX_PTCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x30))
#define AUDMUX_PDCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x34))
#define AUDMUX_CNMCR (*(REG32_PTR_T)(AUDMUX_BASE+0x38))
#define AUDMUX_PTCR_TFS_DIR (1 << 31)
#define AUDMUX_PTCR_TFSEL (0xf << 27)
#define AUDMUX_PTCR_TFSEL_TXFS (0x0 << 27)
#define AUDMUX_PTCR_TFSEL_RXFS (0x8 << 27)
#define AUDMUX_PTCR_TFSEL_PORT1 (0x0 << 27)
#define AUDMUX_PTCR_TFSEL_PORT2 (0x1 << 27)
#define AUDMUX_PTCR_TFSEL_PORT3 (0x2 << 27)
#define AUDMUX_PTCR_TFSEL_PORT4 (0x3 << 27)
#define AUDMUX_PTCR_TFSEL_PORT5 (0x4 << 27)
#define AUDMUX_PTCR_TFSEL_PORT6 (0x5 << 27)
#define AUDMUX_PTCR_TFSEL_PORT7 (0x6 << 27)
#define AUDMUX_PTCR_TCLKDIR (1 << 26)
#define AUDMUX_PTCR_TCSEL (0xf << 22)
#define AUDMUX_PTCR_TCSEL_TXFS (0x0 << 22)
#define AUDMUX_PTCR_TCSEL_RXFS (0x8 << 22)
#define AUDMUX_PTCR_TCSEL_PORT1 (0x0 << 22)
#define AUDMUX_PTCR_TCSEL_PORT2 (0x1 << 22)
#define AUDMUX_PTCR_TCSEL_PORT3 (0x2 << 22)
#define AUDMUX_PTCR_TCSEL_PORT4 (0x3 << 22)
#define AUDMUX_PTCR_TCSEL_PORT5 (0x4 << 22)
#define AUDMUX_PTCR_TCSEL_PORT6 (0x5 << 22)
#define AUDMUX_PTCR_TCSEL_PORT7 (0x6 << 22)
#define AUDMUX_PTCR_RFSDIR (1 << 21)
#define AUDMUX_PTCR_RFSSEL (0xf << 17)
#define AUDMUX_PTCR_RFSSEL_TXFS (0x0 << 17)
#define AUDMUX_PTCR_RFSSEL_RXFS (0x8 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT1 (0x0 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT2 (0x1 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT3 (0x2 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT4 (0x3 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT5 (0x4 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT6 (0x5 << 17)
#define AUDMUX_PTCR_RFSSEL_PORT7 (0x6 << 17)
#define AUDMUX_PTCR_RCLKDIR (1 << 16)
#define AUDMUX_PTCR_RCSEL (0xf << 12)
#define AUDMUX_PTCR_RCSEL_TXFS (0x0 << 12)
#define AUDMUX_PTCR_RCSEL_RXFS (0x8 << 12)
#define AUDMUX_PTCR_RCSEL_PORT1 (0x0 << 12)
#define AUDMUX_PTCR_RCSEL_PORT2 (0x1 << 12)
#define AUDMUX_PTCR_RCSEL_PORT3 (0x2 << 12)
#define AUDMUX_PTCR_RCSEL_PORT4 (0x3 << 12)
#define AUDMUX_PTCR_RCSEL_PORT5 (0x4 << 12)
#define AUDMUX_PTCR_RCSEL_PORT6 (0x5 << 12)
#define AUDMUX_PTCR_RCSEL_PORT7 (0x6 << 12)
#define AUDMUX_PTCR_SYN (1 << 11)
#define AUDMUX_PDCR_RXDSEL (0x7 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT1 (0 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT2 (1 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT3 (2 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT4 (3 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT5 (4 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT6 (5 << 13)
#define AUDMUX_PDCR_RXDSEL_PORT7 (6 << 13)
#define AUDMUX_PDCR_TXRXEN (1 << 12)
#define AUDMUX_CNMCR_BEN (1 << 18)
#define AUDMUX_CNMCR_FSPOL (1 << 17)
#define AUDMUX_CNMCR_CLKPOL (1 << 16)
#define AUDMUX_CNMCR_CNTHI (0xff << 8)
#define AUDMUX_CNMCR_CNTHIw(x) (((x) << 8) & AUDMUX_CNMCR_CNTHI)
#define AUDMUX_CNMCR_CNTLOW (0xff << 0)
#define AUDMUX_CNMCR_CNTLOWw(x) (((x) << 0) & AUDMUX_CNMCR_CNTLOW)
/* SSI */
#define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
#define SSI_STX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04))
#define SSI_SRX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08))
#define SSI_SRX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C))
#define SSI_SCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10))
#define SSI_SISR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14))
#define SSI_SIER1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18))
#define SSI_STCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C))
#define SSI_SRCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20))
#define SSI_STCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24))
#define SSI_SRCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28))
#define SSI_SFCSR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C))
#define SSI_SACNT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38))
#define SSI_SACADD1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C))
#define SSI_SACDAT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40))
#define SSI_SATAG1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44))
#define SSI_STMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48))
#define SSI_SRMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C))
#define SSI_STX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00))
#define SSI_STX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04))
#define SSI_SRX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08))
#define SSI_SRX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C))
#define SSI_SCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10))
#define SSI_SISR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14))
#define SSI_SIER2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18))
#define SSI_STCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C))
#define SSI_SRCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20))
#define SSI_STCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24))
#define SSI_SRCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28))
#define SSI_SFCSR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C))
#define SSI_SACNT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38))
#define SSI_SACADD2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C))
#define SSI_SACDAT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40))
#define SSI_SATAG2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44))
#define SSI_STMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48))
#define SSI_SRMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C))
/* SSI SCR */
#define SSI_SCR_CLK_IST (0x1 << 9)
#define SSI_SCR_TCHN_EN (0x1 << 8)
#define SSI_SCR_SYS_CLK_EN (0x1 << 7)
#define SSI_SCR_I2S_MODE (0x3 << 5)
#define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5)
#define SSI_SCR_I2S_MODE_MASTER (0x1 << 5)
#define SSI_SCR_I2S_MODE_SLAVE (0x2 << 5)
#define SSI_SCR_I2S_MODE_NOR2 (0x3 << 5)
#define SSI_SCR_SYN (0x1 << 4)
#define SSI_SCR_NET (0x1 << 3)
#define SSI_SCR_RE (0x1 << 2)
#define SSI_SCR_TE (0x1 << 1)
#define SSI_SCR_SSIEN (0x1 << 0)
/* SSI SISR */
#define SSI_SISR_CMDAU (0x1 << 18)
#define SSI_SISR_CMDDU (0x1 << 17)
#define SSI_SISR_RXT (0x1 << 16)
#define SSI_SISR_RDR1 (0x1 << 15)
#define SSI_SISR_RDR0 (0x1 << 14)
#define SSI_SISR_TDE1 (0x1 << 13)
#define SSI_SISR_TDE0 (0x1 << 12)
#define SSI_SISR_ROE1 (0x1 << 11)
#define SSI_SISR_ROE0 (0x1 << 10)
#define SSI_SISR_TUE1 (0x1 << 9)
#define SSI_SISR_TUE0 (0x1 << 8)
#define SSI_SISR_TFS (0x1 << 7)
#define SSI_SISR_RFS (0x1 << 6)
#define SSI_SISR_TLS (0x1 << 5)
#define SSI_SISR_RLS (0x1 << 4)
#define SSI_SISR_RFF1 (0x1 << 3)
#define SSI_SISR_RFF2 (0x1 << 2)
#define SSI_SISR_TFE1 (0x1 << 1)
#define SSI_SISR_TFE0 (0x1 << 0)
/* SSI SIER */
#define SSI_SIER_RDMAE (0x1 << 22)
#define SSI_SIER_RIE (0x1 << 21)
#define SSI_SIER_TDMAE (0x1 << 20)
#define SSI_SIER_TIE (0x1 << 19)
#define SSI_SIER_CMDAU (0x1 << 18)
#define SSI_SIER_CMDDU (0x1 << 17)
#define SSI_SIER_RXT (0x1 << 16)
#define SSI_SIER_RDR1 (0x1 << 15)
#define SSI_SIER_RDR0 (0x1 << 14)
#define SSI_SIER_TDE1 (0x1 << 13)
#define SSI_SIER_TDE0 (0x1 << 12)
#define SSI_SIER_ROE1 (0x1 << 11)
#define SSI_SIER_ROE0 (0x1 << 10)
#define SSI_SIER_TUE1 (0x1 << 9)
#define SSI_SIER_TUE0 (0x1 << 8)
#define SSI_SIER_TFS (0x1 << 7)
#define SSI_SIER_RFS (0x1 << 6)
#define SSI_SIER_TLS (0x1 << 5)
#define SSI_SIER_RLS (0x1 << 4)
#define SSI_SIER_RFF1 (0x1 << 3)
#define SSI_SIER_RFF2 (0x1 << 2)
#define SSI_SIER_TFE1 (0x1 << 1)
#define SSI_SIER_TFE0 (0x1 << 0)
/* SSI STCR */
#define SSI_STCR_TXBIT0 (0x1 << 9)
#define SSI_STCR_TFEN1 (0x1 << 8)
#define SSI_STCR_TFEN0 (0x1 << 7)
#define SSI_STCR_TFDIR (0x1 << 6)
#define SSI_STCR_TXDIR (0x1 << 5)
#define SSI_STCR_TSHFD (0x1 << 4)
#define SSI_STCR_TSCKP (0x1 << 3)
#define SSI_STCR_TFSI (0x1 << 2)
#define SSI_STCR_TFSL (0x1 << 1)
#define SSI_STCR_TEFS (0x1 << 0)
/* SSI SRCR */
#define SSI_SRCR_RXEXT (0x1 << 10)
#define SSI_SRCR_RXBIT0 (0x1 << 9)
#define SSI_SRCR_RFEN1 (0x1 << 8)
#define SSI_SRCR_RFEN0 (0x1 << 7)
#define SSI_SRCR_RFDIR (0x1 << 6)
#define SSI_SRCR_RXDIR (0x1 << 5)
#define SSI_SRCR_RSHFD (0x1 << 4)
#define SSI_SRCR_RSCKP (0x1 << 3)
#define SSI_SRCR_RFSI (0x1 << 2)
#define SSI_SRCR_RFSL (0x1 << 1)
#define SSI_SRCR_REFS (0x1 << 0)
/* SSI STCCR/SRCCR */
#define SSI_STRCCR_DIV2 (0x1 << 18)
#define SSI_STRCCR_PSR (0x1 << 17)
#define SSI_STRCCR_WL (0xf << 13)
#define SSI_STRCCR_WL8 (0x3 << 13)
#define SSI_STRCCR_WL10 (0x4 << 13)
#define SSI_STRCCR_WL12 (0x5 << 13)
#define SSI_STRCCR_WL16 (0x7 << 13)
#define SSI_STRCCR_WL18 (0x8 << 13)
#define SSI_STRCCR_WL20 (0x9 << 13)
#define SSI_STRCCR_WL22 (0xa << 13)
#define SSI_STRCCR_WL24 (0xb << 13)
#define SSI_STRCCR_DC (0x1f << 8)
#define SSI_STRCCR_DCw(x) (((x) << 8) & SSI_STRCCR_DC)
#define SSI_STRCCR_DCr(x) (((x) & SSI_SRCCR_DC) >> 8)
#define SSI_STRCCR_PM (0xf << 0)
#define SSI_STRCCR_PMw(x) (((x) << 0) & SSI_STRCCR_PM)
#define SSI_STRCCR_PMr(x) (((x) & SSI_SRCCR_PM) >> 0)
/* SSI SFCSR */
#define SSI_SFCSR_RFCNT1 (0xf << 28)
#define SSI_SFCSR_RFCNT1w(x) (((x) << 28) & SSI_SFCSR_RFCNT1)
#define SSI_SFCSR_RFCNT1r(x) (((x) & SSI_SFCSR_RFCNT1) >> 28)
#define SSI_SFCSR_TFCNT1 (0xf << 24)
#define SSI_SFCSR_TFCNT1w(x) (((x) << 24) & SSI_SFCSR_TFCNT1)
#define SSI_SFCSR_TFCNT1r(x) (((x) & SSI_SFCSR_TFCNT1) >> 24)
#define SSI_SFCSR_RFWM1 (0xf << 20)
#define SSI_SFCSR_RFWM1w(x) (((x) << 20) & SSI_SFCSR_RFWM1)
#define SSI_SFCSR_RFWM1r(x) (((x) & SSI_SFCSR_RFWM1) >> 20)
#define SSI_SFCSR_RFWM1_1 (0x1 << 20)
#define SSI_SFCSR_RFWM1_2 (0x2 << 20)
#define SSI_SFCSR_RFWM1_3 (0x3 << 20)
#define SSI_SFCSR_RFWM1_4 (0x4 << 20)
#define SSI_SFCSR_RFWM1_5 (0x5 << 20)
#define SSI_SFCSR_RFWM1_6 (0x6 << 20)
#define SSI_SFCSR_RFWM1_7 (0x7 << 20)
#define SSI_SFCSR_TFWM1 (0xf << 16)
#define SSI_SFCSR_TFWM1w(x) (((x) << 16) & SSI_SFCSR_TFWM1)
#define SSI_SFCSR_TFWM1r(x) (((x) & SSI_SFCSR_TFWM1) >> 16)
#define SSI_SFCSR_RFCNT0 (0xf << 12)
#define SSI_SFCSR_RFCNT0w(x) (((x) << 12) & SSI_SFCSR_RFCNT0)
#define SSI_SFCSR_RFCNT0r(x) (((x) & SSI_SFCSR_RFCNT0) >> 12)
#define SSI_SFCSR_TFCNT0 (0xf << 8)
#define SSI_SFCSR_TFCNT0w(x) (((x) << 8) & SSI_SFCSR_TFCNT0)
#define SSI_SFCSR_TFCNT0r(x) (((x) & SSI_SFCSR_TFCNT0) >> 8)
#define SSI_SFCSR_RFWM0 (0xf << 4)
#define SSI_SFCSR_RFWM0w(x) (((x) << 4) & SSI_SFCSR_RFWM0)
#define SSI_SFCSR_RFWM0r(x) (((x) & SSI_SFCSR_RFWM0) >> 4)
#define SSI_SFCSR_TFWM0 (0xf << 0)
#define SSI_SFCSR_TFWM0w(x) (((x) << 0) & SSI_SFCSR_TFWM0)
#define SSI_SFCSR_TFWM0r(x) (((x) & SSI_SFCSR_TFWM0) >> 0)
/* SACNT */
#define SSI_SACNT_FRDIV (0x3f << 5)
#define SSI_SACNT_FRDIVw(x) (((x) << 5) & SSI_SACNT_FRDIV)
#define SSI_SACNT_FRDIVr(x) (((x) & SSI_SACNT_FRDIV) >> 5)
#define SSI_SACNT_WR (0x1 << 4)
#define SSI_SACNT_RD (0x1 << 3)
#define SSI_SACNT_TIF (0x1 << 2)
#define SSI_SACNT_FV (0x1 << 1)
#define SSI_SACNT_AC97EN (0x1 << 0)
/* RTC */
#define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
#define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
@ -874,6 +1164,123 @@
#define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
/* CCMR */
#define CCMR_L2PG (0x1 << 29)
#define CCMR_VSTBY (0x1 << 28)
#define CCMR_WBEN (0x1 << 27)
#define CCMR_FPMF (0x1 << 26)
#define CCMR_CSCS (0x1 << 25)
#define CCMR_PERCS (0x1 << 24)
#define CCMR_SSI2S (0x3 << 21)
#define CCMR_SSI2S_MCU_CLK (0x0 << 21)
#define CCMR_SSI2S_USB_CLK (0x1 << 21)
#define CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
#define CCMR_SSI1S (0x3 << 18)
#define CCMR_SSI1S_MCU_CLK (0x0 << 18)
#define CCMR_SSI1S_USB_CLK (0x1 << 18)
#define CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
#define CCMR_RAMW (0x3 << 16)
#define CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
#define CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
#define CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
#define CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
#define CCMR_LPM (0x3 << 14)
#define CCMR_LPM_WAIT_MODE (0x0 << 14)
#define CCMR_LPM_DOZE_MODE (0x1 << 14)
#define CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
#define CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
#define CCMR_FIRS (0x3 << 11)
#define CCMR_FIRS_MCU_CLK (0x0 << 11)
#define CCMR_FIRS_USB_CLK (0x1 << 11)
#define CCMR_FIRS_SERIAL_CLK (0x2 << 11)
#define CCMR_WAMO (0x1 << 10)
#define CCMR_UPE (0x1 << 9)
#define CCMR_SPE (0x1 << 8)
#define CCMR_MDS (0x1 << 7)
#define CCMR_ROMW (0x3 << 5)
#define CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
#define CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
#define CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
#define CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
#define CCMR_SBYCS (0x1 << 4)
#define CCMR_MPE (0x1 << 3)
#define CCMR_PRCS (0x3 << 1)
#define CCMR_PRCS_FPM (0x1 << 1)
#define CCMR_PRCS_CKIH (0x2 << 1)
#define CCMR_FPME (0x1 << 0)
/* PDR0 */
#define PDR0_CSI_PODF (0x1ff << 23)
#define PDR0_CSI_PODFw(x) (((x) << 23) & PDR0_CSI_PODF)
#define PDR0_CSI_PODFr(x) (((x) & PDR0_CSI_PODF) >> 23)
#define PDR0_PER_PODF (0x1f << 16)
#define PDR0_PER_PODFw(x) (((x) << 16) & PDR0_PER_PODF)
#define PDR0_PER_PODFr(x) (((x) & PDR0_PER_PODF) >> 16)
#define PDR0_HSP_PODF (0x7 << 11)
#define PDR0_HSP_PODFw(x) (((x) << 11) & PDR0_HSP_PODF)
#define PDR0_HSP_PODFr(x) (((x) & PDR0_HSP_PODF) >> 11)
#define PDR0_NFC_PODF (0x7 << 8)
#define PDR0_NFC_PODFw(x) (((x) << 8) & PDR0_NFC_PODF)
#define PDR0_NFC_PODFr(x) (((x) & PDR0_NFC_PODF) >> 8)
#define PDR0_IPG_PODF (0x3 << 6)
#define PDR0_IPG_PODFw(x) (((x) << 6) & PDR0_IPG_PODF)
#define PDR0_IPG_PODFr(x) (((x) & PDR0_IPG_PODF) >> 6)
#define PDR0_MAX_PODF (0x7 << 3)
#define PDR0_MAX_PODFw(x) (((x) << 3) & PDR0_MAX_PODF)
#define PDR0_MAX_PODFr(x) (((x) & PDR0_MAX_PODF) >> 3)
#define PDR0_MCU_PODF (0x7 << 0)
#define PDR0_MCU_PODFw(x) (((x) << 0) & PDR0_MCU_PODF)
#define PDR0_MCU_PODFr(x) (((x) & PDR0_MCU_PODF) >> 0)
/* PDR1 */
#define PDR1_USB_PRDF (0x3 << 30)
#define PDR1_USB_PRDFw(x) (((x) << 30) & PDR1_USB_PRDF)
#define PDR1_USB_PRDFr(x) (((x) & PDR1_USB_PRDF) >> 30)
#define PDR1_USB_PODF (0x7 << 27)
#define PDR1_USB_PODFw(x) (((x) << 27) & PDR1_USB_PODF)
#define PDR1_USB_PODFr(x) (((x) & PDR1_USB_PODF) >> 27)
#define PDR1_FIRI_PRE_PODF (0x7 << 24)
#define PDR1_FIRI_PRE_PODFw(x) (((x) << 24) & PDR1_FIRI_PRE_PODF)
#define PDR1_FIRI_PRE_PODFr(x) (((x) & PDR1_FIRI_PRE_PODF) >> 24)
#define PDR1_FIRI_PODF (0x3f << 18)
#define PDR1_FIRI_PODFw(x) (((x) << 18) & PDR1_FIRI_PODF)
#define PDR1_FIRI_PODFr(x) (((x) & PDR1_FIRI_PODF) >> 18)
#define PDR1_SSI2_PRE_PODF (0x7 << 15)
#define PDR1_SSI2_PRE_PODFw(x) (((x) << 15) & PDR1_SSI2_PRE_PODF)
#define PDR1_SSI2_PRE_PODFr(x) (((x) & PDR1_SSI2_PRE_PODF) >> 15)
#define PDR1_SSI2_PODF (0x3f << 9)
#define PDR1_SSI2_PODFw(x) (((x) << 9) & PDR1_SSI2_PODF)
#define PDR1_SSI2_PODFr(x) (((x) & PDR1_SSI2_PODF) >> 9)
#define PDR1_SSI1_PRE_PODF (0x7 << 6)
#define PDR1_SSI1_PRE_PODFw(x) (((x) << 6) & PDR1_SSI1_PRE_PODF)
#define PDR1_SSI1_PRE_PODFr(x) (((x) & PDR1_SSI1_PRE_PODF) >> 6)
#define PDR1_SSI1_PODF (0x3f << 0)
#define PDR1_SSI1_PODFw(x) (((x) << 0) & PDR1_SSI1_PODF)
#define PDR1_SSI1_PODFr(x) (((x) & PDR1_SSI1_PODF) >> 0)
#define CGR0_SD_MMC1(cg) ((cg) << 0*2)
#define CGR0_SD_MMC2(cg) ((cg) << 1*2)
#define CGR0_GPT(cg) ((cg) << 2*2)

875
firmware/export/wm8978.h
View file

@ -21,551 +21,510 @@
#ifndef _WM8978_H
#define _WM8978_H
#define VOLUME_MIN -570
#define VOLUME_MIN -900
#define VOLUME_MAX 60
#define WM8978_I2C_ADDR 0x34
int tenthdb2master(int db);
void audiohw_set_headphone_vol(int vol_l, int vol_r);
#define WMC_I2C_ADDR 0x34
/* Registers */
#define WM8978_SOFTWARE_RESET 0x00
#define WM8978_POWER_MANAGEMENT1 0x01
#define WM8978_POWER_MANAGEMENT2 0x02
#define WM8978_POWER_MANAGEMENT3 0x03
#define WM8978_AUDIO_INTERFACE 0x04
#define WM8978_COMPANDING_CTRL 0x05
#define WM8978_CLOCK_GEN_CTRL 0x06
#define WM8978_ADDITIONAL_CTRL 0x07
#define WM8978_GPIO 0x08
#define WM8978_JACK_DETECT_CONTROL1 0x09
#define WM8978_DAC_CONTROL 0x0a
#define WM8978_LEFT_DAC_DIGITAL_VOL 0x0b
#define WM8978_RIGHT_DAC_DIGITAL_VOL 0x0c
#define WM8978_JACK_DETECT_CONTROL2 0x0d
#define WM8978_ADC_CONTROL 0x0e
#define WM8978_LEFT_ADC_DIGITAL_VOL 0x0f
#define WM8978_RIGHT_ADC_DITIGAL_VOL 0x10
#define WM8978_EQ1_LOW_SHELF 0x12
#define WM8978_EQ2_PEAK1 0x13
#define WM8978_EQ3_PEAK2 0x14
#define WM8978_EQ4_PEAK3 0x15
#define WM8978_EQ5_HIGH_SHELF 0x16
#define WM8978_DAC_LIMITER1 0x18
#define WM8978_DAC_LIMITER2 0x19
#define WM8978_NOTCH_FILTER1 0x1b
#define WM8978_NOTCH_FILTER2 0x1c
#define WM8978_NOTCH_FILTER3 0x1d
#define WM8978_NOTCH_FILTER4 0x1e
#define WM8978_ALC_CONTROL1 0x20
#define WM8978_ALC_CONTROL2 0x21
#define WM8978_ALC_CONTROL3 0x22
#define WM8978_NOISE_GATE 0x23
#define WM8978_PLL_N 0x24
#define WM8978_PLL_K1 0x25
#define WM8978_PLL_K2 0x26
#define WM8978_PLL_K3 0x27
#define WM8978_3D_CONTROL 0x29
#define WM8978_BEEP_CONTROL 0x2b
#define WM8978_INPUT_CTRL 0x2c
#define WM8978_LEFT_INP_PGA_GAIN_CTRL 0x2d
#define WM8978_RIGHT_INP_PGA_GAIN_CTRL 0x2e
#define WM8978_LEFT_ADC_BOOST_CTRL 0x2f
#define WM8978_RIGHT_ADC_BOOST_CTRL 0x30
#define WM8978_OUTPUT_CTRL 0x31
#define WM8978_LEFT_MIXER_CTRL 0x32
#define WM8978_RIGHT_MIXER_CTRL 0x33
#define WM8978_LOUT1_HP_VOLUME_CTRL 0x34
#define WM8978_ROUT1_HP_VOLUME_CTRL 0x35
#define WM8978_LOUT2_SPK_VOLUME_CTRL 0x36
#define WM8978_ROUT2_SPK_VOLUME_CTRL 0x37
#define WM8978_OUT3_MIXER_CTRL 0x38
#define WM8978_OUT4_MONO_MIXER_CTRL 0x39
#define WMC_SOFTWARE_RESET 0x00
#define WMC_POWER_MANAGEMENT1 0x01
#define WMC_POWER_MANAGEMENT2 0x02
#define WMC_POWER_MANAGEMENT3 0x03
#define WMC_AUDIO_INTERFACE 0x04
#define WMC_COMPANDING_CTRL 0x05
#define WMC_CLOCK_GEN_CTRL 0x06
#define WMC_ADDITIONAL_CTRL 0x07
#define WMC_GPIO 0x08
#define WMC_JACK_DETECT_CONTROL1 0x09
#define WMC_DAC_CONTROL 0x0a
#define WMC_LEFT_DAC_DIGITAL_VOL 0x0b
#define WMC_RIGHT_DAC_DIGITAL_VOL 0x0c
#define WMC_JACK_DETECT_CONTROL2 0x0d
#define WMC_ADC_CONTROL 0x0e
#define WMC_LEFT_ADC_DIGITAL_VOL 0x0f
#define WMC_RIGHT_ADC_DIGITAL_VOL 0x10
#define WMC_EQ1_LOW_SHELF 0x12
#define WMC_EQ2_PEAK1 0x13
#define WMC_EQ3_PEAK2 0x14
#define WMC_EQ4_PEAK3 0x15
#define WMC_EQ5_HIGH_SHELF 0x16
#define WMC_DAC_LIMITER1 0x18
#define WMC_DAC_LIMITER2 0x19
#define WMC_NOTCH_FILTER1 0x1b
#define WMC_NOTCH_FILTER2 0x1c
#define WMC_NOTCH_FILTER3 0x1d
#define WMC_NOTCH_FILTER4 0x1e
#define WMC_ALC_CONTROL1 0x20
#define WMC_ALC_CONTROL2 0x21
#define WMC_ALC_CONTROL3 0x22
#define WMC_NOISE_GATE 0x23
#define WMC_PLL_N 0x24
#define WMC_PLL_K1 0x25
#define WMC_PLL_K2 0x26
#define WMC_PLL_K3 0x27
#define WMC_3D_CONTROL 0x29
#define WMC_BEEP_CONTROL 0x2b
#define WMC_INPUT_CTRL 0x2c
#define WMC_LEFT_INP_PGA_GAIN_CTRL 0x2d
#define WMC_RIGHT_INP_PGA_GAIN_CTRL 0x2e
#define WMC_LEFT_ADC_BOOST_CTRL 0x2f
#define WMC_RIGHT_ADC_BOOST_CTRL 0x30
#define WMC_OUTPUT_CTRL 0x31
#define WMC_LEFT_MIXER_CTRL 0x32
#define WMC_RIGHT_MIXER_CTRL 0x33
#define WMC_LOUT1_HP_VOLUME_CTRL 0x34
#define WMC_ROUT1_HP_VOLUME_CTRL 0x35
#define WMC_LOUT2_SPK_VOLUME_CTRL 0x36
#define WMC_ROUT2_SPK_VOLUME_CTRL 0x37
#define WMC_OUT3_MIXER_CTRL 0x38
#define WMC_OUT4_MONO_MIXER_CTRL 0x39
#define WMC_NUM_REGISTERS 0x3a
/* Register bitmasks */
/* WM8978_SOFTWARE_RESET (0x00) */
#define WM8978_RESET
/* Volume update bit for volume registers */
#define WMC_VU (1 << 8)
/* Zero-crossing bit for volume registers */
#define WMC_ZC (1 << 7)
/* Mute bit for volume registers */
#define WMC_MUTE (1 << 6)
/* Volume masks and macros for digital volumes */
#define WMC_DVOL 0xff
#define WMC_DVOLr(x) ((x) & WMC_DVOL)
#define WMC_DVOLw(x) ((x) & WMC_DVOL)
/* Volums masks and macros for analogue volumes */
#define WMC_AVOL 0x3f
#define WMC_AVOLr(x) ((x) & WMC_AVOLUME_MASK)
#define WMC_AVOLw(x) ((x) & WMC_AVOLUME_MASK)
/* WMC_SOFTWARE_RESET (0x00) */
#define WMC_RESET
/* Write any value */
/* WM8978_POWER_MANAGEMENT1 (0x01) */
#define WM8978_BUFDCOMPEN (1 << 8)
#define WM8978_OUT4MIXEN (1 << 7)
#define WM8978_OUT3MIXEN (1 << 6)
#define WM8978_PLLEN (1 << 5)
#define WM8978_MICBEN (1 << 4)
#define WM8978_BIASEN (1 << 3)
#define WM8978_BUFIOEN (1 << 2)
#define WM8978_VMIDSEL (3 << 0)
#define WM8978_VMIDSEL_OFF (0 << 0)
#define WM8978_VMIDSEL_75K (1 << 0)
#define WM8978_VMIDSEL_300K (2 << 0)
#define WM8978_VMIDSEL_5K (3 << 0)
/* WMC_POWER_MANAGEMENT1 (0x01) */
#define WMC_BUFDCOMPEN (1 << 8)
#define WMC_OUT4MIXEN (1 << 7)
#define WMC_OUT3MIXEN (1 << 6)
#define WMC_PLLEN (1 << 5)
#define WMC_MICBEN (1 << 4)
#define WMC_BIASEN (1 << 3)
#define WMC_BUFIOEN (1 << 2)
#define WMC_VMIDSEL (3 << 0)
#define WMC_VMIDSEL_OFF (0 << 0)
#define WMC_VMIDSEL_75K (1 << 0)
#define WMC_VMIDSEL_300K (2 << 0)
#define WMC_VMIDSEL_5K (3 << 0)
/* WM8978_POWER_MANAGEMENT2 (0x02) */
#define WM8978_ROUT1EN (1 << 8)
#define WM8978_LOUT1EN (1 << 7)
#define WM8978_SLEEP (1 << 6)
#define WM8978_BOOSTENR (1 << 5)
#define WM8978_BOOSTENL (1 << 4)
#define WM8978_INPPGAENR (1 << 3)
#define WM8978_INPPGAENL (1 << 2)
#define WM8978_ADCENR (1 << 1)
#define WM8978_ADCENL (1 << 0)
/* WMC_POWER_MANAGEMENT2 (0x02) */
#define WMC_ROUT1EN (1 << 8)
#define WMC_LOUT1EN (1 << 7)
#define WMC_SLEEP (1 << 6)
#define WMC_BOOSTENR (1 << 5)
#define WMC_BOOSTENL (1 << 4)
#define WMC_INPPGAENR (1 << 3)
#define WMC_INPPGAENL (1 << 2)
#define WMC_ADCENR (1 << 1)
#define WMC_ADCENL (1 << 0)
/* WM8978_POWER_MANAGEMENT3 (0x03) */
#define WM8978_OUT4EN (1 << 8)
#define WM8978_OUT3EN (1 << 7)
#define WM8978_LOUT2EN (1 << 6)
#define WM8978_ROUT2EN (1 << 5)
#define WM8978_RMIXEN (1 << 3)
#define WM8978_LMIXEN (1 << 2)
#define WM8978_DACENR (1 << 1)
#define WM8978_DACENL (1 << 0)
/* WMC_POWER_MANAGEMENT3 (0x03) */
#define WMC_OUT4EN (1 << 8)
#define WMC_OUT3EN (1 << 7)
#define WMC_LOUT2EN (1 << 6)
#define WMC_ROUT2EN (1 << 5)
#define WMC_RMIXEN (1 << 3)
#define WMC_LMIXEN (1 << 2)
#define WMC_DACENR (1 << 1)
#define WMC_DACENL (1 << 0)
/* WM8978_AUDIO_INTERFACE (0x04) */
#define WM8978_BCP (1 << 8)
#define WM8978_LRP (1 << 7)
#define WM8978_WL (3 << 5)
#define WM8978_WL_16 (0 << 5)
#define WM8978_WL_20 (1 << 5)
#define WM8978_WL_24 (2 << 5)
#define WM8978_WL_32 (3 << 5)
#define WM8978_FMT (3 << 3)
#define WM8978_FMT_RJUST (0 << 3)
#define WM8978_FMT_LJUST (1 << 3)
#define WM8978_FMT_I2S (2 << 3)
#define WM8978_FMT_DSP_PCM (3 << 3)
#define WM8978_DACLRSWAP (1 << 2)
#define WM8978_ADCLRSWAP (1 << 1)
#define WM8978_MONO (1 << 0)
/* WMC_AUDIO_INTERFACE (0x04) */
#define WMC_BCP (1 << 8)
#define WMC_LRP (1 << 7)
#define WMC_WL (3 << 5)
#define WMC_WL_16 (0 << 5)
#define WMC_WL_20 (1 << 5)
#define WMC_WL_24 (2 << 5)
#define WMC_WL_32 (3 << 5)
#define WMC_FMT (3 << 3)
#define WMC_FMT_RJUST (0 << 3)
#define WMC_FMT_LJUST (1 << 3)
#define WMC_FMT_I2S (2 << 3)
#define WMC_FMT_DSP_PCM (3 << 3)
#define WMC_DACLRSWAP (1 << 2)
#define WMC_ADCLRSWAP (1 << 1)
#define WMC_MONO (1 << 0)
/* WM8978_COMPANDING_CTRL (0x05) */
#define WM8978_WL8 (1 << 5)
#define WM8978_DAC_COMP (3 << 3)
#define WM8978_DAC_COMP_OFF (0 << 3)
#define WM8978_DAC_COMP_U_LAW (2 << 3)
#define WM8978_DAC_COMP_A_LAW (3 << 3)
#define WM8978_ADC_COMP (3 << 1)
#define WM8978_ADC_COMP_OFF (0 << 1)
#define WM8978_ADC_COMP_U_LAW (2 << 1)
#define WM8978_ADC_COMP_A_LAW (3 << 1)
#define WM8978_LOOPBACK (1 << 0)
/* WMC_COMPANDING_CTRL (0x05) */
#define WMC_WL8 (1 << 5)
#define WMC_DAC_COMP (3 << 3)
#define WMC_DAC_COMP_OFF (0 << 3)
#define WMC_DAC_COMP_U_LAW (2 << 3)
#define WMC_DAC_COMP_A_LAW (3 << 3)
#define WMC_ADC_COMP (3 << 1)
#define WMC_ADC_COMP_OFF (0 << 1)
#define WMC_ADC_COMP_U_LAW (2 << 1)
#define WMC_ADC_COMP_A_LAW (3 << 1)
#define WMC_LOOPBACK (1 << 0)
/* WM8978_CLOCK_GEN_CTRL (0x06) */
#define WM8978_CLKSEL (1 << 8)
#define WM8978_MCLKDIV (7 << 5)
#define WM8978_MCLKDIV_1 (0 << 5)
#define WM8978_MCLKDIV_1_5 (1 << 5)
#define WM8978_MCLKDIV_2 (2 << 5)
#define WM8978_MCLKDIV_3 (3 << 5)
#define WM8978_MCLKDIV_4 (4 << 5)
#define WM8978_MCLKDIV_6 (5 << 5)
#define WM8978_MCLKDIV_8 (6 << 5)
#define WM8978_MCLKDIV_12 (7 << 5)
#define WM8978_BCLKDIV (7 << 2)
#define WM8978_BCLKDIV_1 (0 << 2)
#define WM8978_BCLKDIV_2 (1 << 2)
#define WM8978_BCLKDIV_4 (2 << 2)
#define WM8978_BCLKDIV_8 (3 << 2)
#define WM8978_BCLKDIV_16 (4 << 2)
#define WM8978_BCLKDIV_32 (5 << 2)
#define WM8978_MS (1 << 0)
/* WMC_CLOCK_GEN_CTRL (0x06) */
#define WMC_CLKSEL (1 << 8)
#define WMC_MCLKDIV (7 << 5)
#define WMC_MCLKDIV_1 (0 << 5)
#define WMC_MCLKDIV_1_5 (1 << 5)
#define WMC_MCLKDIV_2 (2 << 5)
#define WMC_MCLKDIV_3 (3 << 5)
#define WMC_MCLKDIV_4 (4 << 5)
#define WMC_MCLKDIV_6 (5 << 5)
#define WMC_MCLKDIV_8 (6 << 5)
#define WMC_MCLKDIV_12 (7 << 5)
#define WMC_BCLKDIV (7 << 2)
#define WMC_BCLKDIV_1 (0 << 2)
#define WMC_BCLKDIV_2 (1 << 2)
#define WMC_BCLKDIV_4 (2 << 2)
#define WMC_BCLKDIV_8 (3 << 2)
#define WMC_BCLKDIV_16 (4 << 2)
#define WMC_BCLKDIV_32 (5 << 2)
#define WMC_MS (1 << 0)
/* WM8978_ADDITIONAL_CTRL (0x07) */
#define WM8978_SR (7 << 1)
#define WM8978_SLOWCLKEN (1 << 0)
/* WMC_ADDITIONAL_CTRL (0x07) */
/* This configure the digital filter coefficients - pick the closest
* to what's really being used (greater than or equal). */
#define WMC_SR (7 << 1)
#define WMC_SR_48KHZ (0 << 1)
#define WMC_SR_32KHZ (1 << 1)
#define WMC_SR_24KHZ (2 << 1)
#define WMC_SR_16KHZ (3 << 1)
#define WMC_SR_12KHZ (4 << 1)
#define WMC_SR_8KHZ (5 << 1)
/* 110-111=reserved */
#define WMC_SLOWCLKEN (1 << 0)
/* WM8978_GPIO (0x08) */
#define WM8978_OPCLKDIV (3 << 4)
#define WM8978_OPCLKDIV_1 (0 << 4)
#define WM8978_OPCLKDIV_2 (1 << 4)
#define WM8978_OPCLKDIV_3 (2 << 4)
#define WM8978_OPCLKDIV_4 (3 << 4)
#define WM8978_GPIO1POL (1 << 3)
#define WM8978_GPIO1SEL (7 << 0)
#define WM8978_GPIO1SEL_TEMP_OK (2 << 0)
#define WM8978_GPIO1SEL_AMUTE_ACTIVE (3 << 0)
#define WM8978_GPIO1SEL_PLL_CLK_OP (4 << 0)
#define WM8978_GPIO1SEL_PLL_LOCK (5 << 0)
#define WM8978_GPIO1SEL_LOGIC_1 (6 << 0)
#define WM8978_GPIO1SEL_LOGIC_0 (7 << 0)
/* WMC_GPIO (0x08) */
#define WMC_OPCLKDIV (3 << 4)
#define WMC_OPCLKDIV_1 (0 << 4)
#define WMC_OPCLKDIV_2 (1 << 4)
#define WMC_OPCLKDIV_3 (2 << 4)
#define WMC_OPCLKDIV_4 (3 << 4)
#define WMC_GPIO1POL (1 << 3)
#define WMC_GPIO1SEL (7 << 0)
#define WMC_GPIO1SEL_TEMP_OK (2 << 0)
#define WMC_GPIO1SEL_AMUTE_ACTIVE (3 << 0)
#define WMC_GPIO1SEL_PLL_CLK_OP (4 << 0)
#define WMC_GPIO1SEL_PLL_LOCK (5 << 0)
#define WMC_GPIO1SEL_LOGIC_1 (6 << 0)
#define WMC_GPIO1SEL_LOGIC_0 (7 << 0)
/* WM8978_JACK_DETECT_CONTROL1 (0x09) */
#define WM8978_JD_VMID (3 << 7)
#define WM8978_JD_VMID_EN_0 (1 << 7)
#define WM8978_JD_VMID_EN_1 (2 << 7)
#define WM8978_JD_EN (1 << 6)
#define WM8978_JD_SEL (3 << 4)
#define WM8978_JD_SEL_GPIO1 (0 << 4)
#define WM8978_JD_SEL_GPIO2 (1 << 4)
#define WM8978_JD_SEL_GPIO3 (2 << 4)
/* WMC_JACK_DETECT_CONTROL1 (0x09) */
#define WMC_JD_VMID (3 << 7)
#define WMC_JD_VMID_EN_0 (1 << 7)
#define WMC_JD_VMID_EN_1 (2 << 7)
#define WMC_JD_EN (1 << 6)
#define WMC_JD_SEL (3 << 4)
#define WMC_JD_SEL_GPIO1 (0 << 4)
#define WMC_JD_SEL_GPIO2 (1 << 4)
#define WMC_JD_SEL_GPIO3 (2 << 4)
/* WM8978_DAC_CONTROL (0x0a) */
#define WM8978_SOFT_MUTE (1 << 6)
#define WM8978_DACOSR_128 (1 << 3)
#define WM8978_AMUTE (1 << 2)
#define WM8978_DACPOLR (1 << 1)
#define WM8978_DACPOLL (1 << 0)
/* WMC_DAC_CONTROL (0x0a) */
#define WMC_SOFT_MUTE (1 << 6)
#define WMC_DACOSR_128 (1 << 3)
#define WMC_AMUTE (1 << 2)
#define WMC_DACPOLR (1 << 1)
#define WMC_DACPOLL (1 << 0)
/* WM8978_LEFT_DAC_DIGITAL_VOL (0x0b) */
#define WM8978_DACVUL (1 << 8)
/* WMC_LEFT_DAC_DIGITAL_VOL (0x0b) */
/* WMC_RIGHT_DAC_DIGITAL_VOL (0x0c) */
/* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */
#define WM8978_DACVOLL (0xff << 0)
#define WM8978_DACVOLLr(x) ((x) & WM8978_DACVOLL)
#define WM8978_DACVOLLw(x) ((x) & WM8978_DACVOLL)
/* Use WMC_DVOL* macros */
/* WM8978_RIGHT_DAC_DIGITAL_VOL (0x0c) */
#define WM8978_DACVUR (1 << 8)
/* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */
#define WM8978_DACVOLR (0xff << 0)
#define WM8978_DACVOLRr(x) ((x) & WM8978_DACVOLR)
#define WM8978_DACVOLRw(x) ((x) & WM8978_DACVOLR)
/* WMC_JACK_DETECT_CONTROL2 (0x0d) */
#define WMC_JD_EN1 (0xf << 4)
#define WMC_OUT1_EN1 (1 << 4)
#define WMC_OUT2_EN1 (2 << 4)
#define WMC_OUT3_EN1 (4 << 4)
#define WMC_OUT4_EN1 (8 << 4)
#define WMC_JD_EN0 (0xf << 0)
#define WMC_OUT1_EN0 (1 << 0)
#define WMC_OUT2_EN0 (2 << 0)
#define WMC_OUT3_EN0 (4 << 0)
#define WMC_OUT4_EN0 (8 << 0)
/* WM8978_JACK_DETECT_CONTROL2 (0x0d) */
#define WM8978_JD_EN1 (0xf << 4)
#define WM8978_OUT1_EN1 (1 << 4)
#define WM8978_OUT2_EN1 (2 << 4)
#define WM8978_OUT3_EN1 (4 << 4)
#define WM8978_OUT4_EN1 (8 << 4)
#define WM8978_JD_EN0 (0xf << 0)
#define WM8978_OUT1_EN0 (1 << 0)
#define WM8978_OUT2_EN0 (2 << 0)
#define WM8978_OUT3_EN0 (4 << 0)
#define WM8978_OUT4_EN0 (8 << 0)
/* WMC_ADC_CONTROL (0x0e) */
#define WMC_HPFEN (1 << 8)
#define WMC_HPFAPP (1 << 7)
#define WMC_HPFCUT (7 << 4)
#define WMC_ADCOSR (1 << 3)
#define WMC_ADCRPOL (1 << 1)
#define WMC_ADCLPOL (1 << 0)
/* WM8978_ADC_CONTROL (0x0e) */
#define WM8978_HPFEN (1 << 8)
#define WM8978_HPFAPP (1 << 7)
#define WM8978_HPFCUT (7 << 4)
#define WM8978_ADCOSR (1 << 3)
#define WM8978_ADCRPOL (1 << 1)
#define WM8978_ADCLPOL (1 << 0)
/* WM8978_LEFT_ADC_DIGITAL_VOL (0x0f) */
/* WM8978_RIGHT_ADC_DITIGAL_VOL (0x10) */
#define WM8978_ADCVU (1 << 8)
/* WMC_LEFT_ADC_DIGITAL_VOL (0x0f) */
/* WMC_RIGHT_ADC_DITIGAL_VOL (0x10) */
/* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */
#define WM8978_ADCVOL (0xff << 0)
#define WM8978_ADCVOLr(x) ((x) & 0xff)
#define WM8978_ADCVOLw(x) ((x) & 0xff)
/*Use WMC_DVOL* macros */
/* WM8978_EQ1_LOW_SHELF (0x12) */
#define WM8978_EQ3DMODE (1 << 8)
#define WM8978_EQ1C (3 << 5) /* Cutoff */
#define WM8978_EQ1C_80HZ (0 << 5) /* 80Hz */
#define WM8978_EQ1C_105HZ (1 << 5) /* 105Hz */
#define WM8978_EQ1C_135HZ (2 << 5) /* 135Hz */
#define WM8978_EQ1C_175HZ (3 << 5) /* 175Hz */
/* Macros for EQ gain and cutoff */
#define WMC_EQGC 0x1f
#define WMC_EQGCr(x) ((x) & WMC_EQGC)
#define WMC_EQGCw(x) ((x) & WMC_EQGC)
/* WMC_EQ1_LOW_SHELF (0x12) */
#define WMC_EQ3DMODE (1 << 8)
#define WMC_EQ1C (3 << 5) /* Cutoff */
#define WMC_EQ1C_80HZ (0 << 5) /* 80Hz */
#define WMC_EQ1C_105HZ (1 << 5) /* 105Hz */
#define WMC_EQ1C_135HZ (2 << 5) /* 135Hz */
#define WMC_EQ1C_175HZ (3 << 5) /* 175Hz */
/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */
#define WM8978_EQ1G (0x1f << 0)
#define WM8978_EQ1Gr(x) ((x) & WM8978_EQ1G)
#define WM8978_EQ1Gw(x) ((x) & WM8978_EQ1G)
/* WM8978_EQ2_PEAK1 (0x13) */
#define WM8978_EQ2BW (1 << 8)
#define WM8978_EQ2C (3 << 5) /* Center */
#define WM8978_EQ2C_230HZ (0 << 5) /* 230Hz */
#define WM8978_EQ2C_300HZ (1 << 5) /* 300Hz */
#define WM8978_EQ2C_385HZ (2 << 5) /* 385Hz */
#define WM8978_EQ2C_500HZ (3 << 5) /* 500Hz */
/* WMC_EQ2_PEAK1 (0x13) */
#define WMC_EQ2BW (1 << 8)
#define WMC_EQ2C (3 << 5) /* Center */
#define WMC_EQ2C_230HZ (0 << 5) /* 230Hz */
#define WMC_EQ2C_300HZ (1 << 5) /* 300Hz */
#define WMC_EQ2C_385HZ (2 << 5) /* 385Hz */
#define WMC_EQ2C_500HZ (3 << 5) /* 500Hz */
/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
11001-11111=reserved */
#define WM8978_EQ2G (0x1f << 0)
#define WM8978_EQ2Gr(x) ((x) & WM8978_EQ2G)
#define WM8978_EQ2Gw(x) ((x) & WM8978_EQ2G)
/* WM8978_EQ3_PEAK2 (0x14) */
#define WM8978_EQ3BW (1 << 8)
#define WM8978_EQ3C (3 << 5) /* Center */
#define WM8978_EQ3C_650HZ (0 << 5) /* 650Hz */
#define WM8978_EQ3C_850HZ (1 << 5) /* 850Hz */
#define WM8978_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */
#define WM8978_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */
/* WMC_EQ3_PEAK2 (0x14) */
#define WMC_EQ3BW (1 << 8)
#define WMC_EQ3C (3 << 5) /* Center */
#define WMC_EQ3C_650HZ (0 << 5) /* 650Hz */
#define WMC_EQ3C_850HZ (1 << 5) /* 850Hz */
#define WMC_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */
#define WMC_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */
/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
11001-11111=reserved */
#define WM8978_EQ3G (0x1f << 0)
#define WM8978_EQ3Gr(x) ((x) & WM8978_EQ3G)
#define WM8978_EQ3Gw(x) ((x) & WM8978_EQ3G)
/* WM8978_EQ4_PEAK3 (0x15) */
#define WM8978_EQ4BW (1 << 8)
#define WM8978_EQ4C (3 << 5) /* Center */
#define WM8978_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */
#define WM8978_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */
#define WM8978_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */
#define WM8978_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */
/* WMC_EQ4_PEAK3 (0x15) */
#define WMC_EQ4BW (1 << 8)
#define WMC_EQ4C (3 << 5) /* Center */
#define WMC_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */
#define WMC_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */
#define WMC_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */
#define WMC_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */
/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
11001-11111=reserved */
#define WM8978_EQ4G (0x1f << 0)
#define WM8978_EQ4Gr(x) ((x) & WM8978_EQ4G)
#define WM8978_EQ4Gw(x) ((x) & WM8978_EQ4G)
/* WM8978_EQ5_HIGH_SHELF (0x16) */
#define WM8978_EQ5C (3 << 5) /* Cutoff */
#define WM8978_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */
#define WM8978_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */
#define WM8978_EQ5C_9KHZ (2 << 5) /* 9.0kHz */
#define WM8978_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */
/* WMC_EQ5_HIGH_SHELF (0x16) */
#define WMC_EQ5C (3 << 5) /* Cutoff */
#define WMC_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */
#define WMC_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */
#define WMC_EQ5C_9KHZ (2 << 5) /* 9.0kHz */
#define WMC_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */
/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
11001-11111=reserved */
#define WM8978_EQ5G (0x1f << 0)
#define WM8978_EQ5Gr(x) ((x) & WM8978_EQ5G)
#define WM8978_EQ5Gw(x) ((x) & WM8978_EQ5G)
/* WM8978_DAC_LIMITER1 (0x18) */
#define WM8978_LIMEN (1 << 8)
/* WMC_DAC_LIMITER1 (0x18) */
#define WMC_LIMEN (1 << 8)
/* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */
#define WM8978_LIMDCY (0xf << 4)
#define WM8978_LIMDCYr(x) (((x) & WM8978_LIMDCY) >> 4)
#define WM8978_LIMDCYw(x) (((x) << 4) & WM8978_LIMDCY)
#define WMC_LIMDCY (0xf << 4)
#define WMC_LIMDCYr(x) (((x) & WMC_LIMDCY) >> 4)
#define WMC_LIMDCYw(x) (((x) << 4) & WMC_LIMDCY)
/* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */
#define WM8978_LIMATK (0xf << 0)
#define WM8978_LIMATKr(x) ((x) & WM8978_LIMATK)
#define WM8978_LIMATKw(x) ((x) & WM8978_LIMATK)
#define WMC_LIMATK (0xf << 0)
#define WMC_LIMATKr(x) ((x) & WMC_LIMATK)
#define WMC_LIMATKw(x) ((x) & WMC_LIMATK)
/* WM8978_DAC_LIMITER2 (0x19) */
#define WM8978_LIMLVL (7 << 4)
/* WMC_DAC_LIMITER2 (0x19) */
#define WMC_LIMLVL (7 << 4)
/* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */
#define WM8978_LIMLVLr(x) (((x) & WM8978_LIMLVL) >> 4)
#define WM8978_LIMLVLw(x) (((x) << 4) & WM8978_LIMLVL)
#define WM8978_LIMBOOST (0xf << 0)
#define WMC_LIMLVLr(x) (((x) & WMC_LIMLVL) >> 4)
#define WMC_LIMLVLw(x) (((x) << 4) & WMC_LIMLVL)
#define WMC_LIMBOOST (0xf << 0)
/* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */
#define WM8978_LIMBOOSTr(x) (((x) & WM8978_LIMBOOST)
#define WM8978_LIMBOOSTw(x) (((x) & WM8978_LIMBOOST)
#define WMC_LIMBOOSTr(x) (((x) & WMC_LIMBOOST)
#define WMC_LIMBOOSTw(x) (((x) & WMC_LIMBOOST)
/* WM8978_NOTCH_FILTER1 (0x1b) */
#define WM8978_NFU1 (1 << 8)
#define WM8978_NFEN (1 << 7)
#define WM8978_NFA0_13_7 (0x7f << 0)
#define WM8978_NFA0_13_7r(x) ((x) & WM8978_NFA0_13_7)
#define WM8978_NFA0_13_7w(x) ((x) & WM8978_NFA0_13_7)
/* WM8978_NOTCH_FILTER2 (0x1c) */
#define WM8978_NFU2 (1 << 8)
#define WM8978_NFA0_6_0 (0x7f << 0)
#define WM8978_NFA0_6_0r(x) ((x) & WM8978_NFA0_6_0)
#define WM8978_NFA0_6_0w(x) ((x) & WM8978_NFA0_6_0)
/* Generic notch filter bits and macros */
#define WMC_NFU (1 << 8)
#define WMC_NFA (0x7f << 0)
#define WMC_NFAr(x) ((x) & WMC_NFA)
#define WMC_NFAw(x) ((x) & WMC_NFA)
/* WM8978_NOTCH_FILTER3 (0x1d) */
#define WM8978_NFU3 (1 << 8)
#define WM8978_NFA1_13_7 (0x7f << 0)
#define WM8978_NFA1_13_7r(x) ((x) & WM8978_NFA1_13_7)
#define WM8978_NFA1_13_7w(x) ((x) & WM8978_NFA1_13_7)
/* WMC_NOTCH_FILTER1 (0x1b) */
#define WMC_NFEN (1 << 7)
/* WMC_NOTCH_FILTER2 (0x1c) */
/* WMC_NOTCH_FILTER3 (0x1d) */
/* WMC_NOTCH_FILTER4 (0x1e) */
/* WM8978_NOTCH_FILTER4 (0x1e) */
#define WM8978_NFU4 (1 << 8)
#define WM8978_NFA1_6_0 (0x7f << 0)
#define WM8978_NFA1_6_0r(x) ((x) & WM8978_NFA1_6_0)
#define WM8978_NFA1_6_0w(x) ((x) & WM8978_NFA1_6_0)
/* WM8978_ALC_CONTROL1 (0x20) */
#define WM8978_ALCSEL (3 << 7)
#define WM8978_ALCSEL_OFF (0 << 7)
#define WM8978_ALCSEL_RIGHT_ONLY (1 << 7)
#define WM8978_ALCSEL_LEFT_ONLY (2 << 7)
#define WM8978_ALCSEL_BOTH_ON (3 << 7)
/* WMC_ALC_CONTROL1 (0x20) */
#define WMC_ALCSEL (3 << 7)
#define WMC_ALCSEL_OFF (0 << 7)
#define WMC_ALCSEL_RIGHT_ONLY (1 << 7)
#define WMC_ALCSEL_LEFT_ONLY (2 << 7)
#define WMC_ALCSEL_BOTH_ON (3 << 7)
/* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */
#define WM8978_ALCMAXGAIN (7 << 3)
#define WM8978_ALCMAXGAINr(x) (((x) & WM8978_ALCMAXGAIN) >> 3)
#define WM8978_ALCMAXGAINw(x) (((x) << 3) & WM8978_ALCMAXGAIN)
#define WMC_ALCMAXGAIN (7 << 3)
#define WMC_ALCMAXGAINr(x) (((x) & WMC_ALCMAXGAIN) >> 3)
#define WMC_ALCMAXGAINw(x) (((x) << 3) & WMC_ALCMAXGAIN)
/* 000:-12dB...(6dB steps)...111:+30dB */
#define WM8978_ALCMINGAIN (7 << 0)
#define WM8978_ALCMINGAINr(x) ((x) & WM8978_ALCMINGAIN)
#define WM8978_ALCMINGAINw(x) ((x) & WM8978_ALCMINGAIN)
#define WMC_ALCMINGAIN (7 << 0)
#define WMC_ALCMINGAINr(x) ((x) & WMC_ALCMINGAIN)
#define WMC_ALCMINGAINw(x) ((x) & WMC_ALCMINGAIN)
/* WM8978_ALC_CONTROL2 (0x21) */
/* WMC_ALC_CONTROL2 (0x21) */
/* 0000=0ms, 0001=2.67ms, 0010=5.33ms...
(2x with every step)...43.691s */
#define WM8978_ALCHLD (0xf << 4)
#define WM8978_ALCHLDr(x) (((x) & WM8978_ALCHLD) >> 4)
#define WM8978_ALCHLDw(x) (((x) << 4) & WM8978_ALCHLD)
#define WMC_ALCHLD (0xf << 4)
#define WMC_ALCHLDr(x) (((x) & WMC_ALCHLD) >> 4)
#define WMC_ALCHLDw(x) (((x) << 4) & WMC_ALCHLD)
/* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS...
(-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */
#define WM8978_ALCLVL (0xf << 0)
#define WM8978_ALCLVLr(x) ((x) & WM8978_ALCLVL)
#define WM8978_ALCLVLw(x) ((x) & WM8978_ALCLVL)
#define WMC_ALCLVL (0xf << 0)
#define WMC_ALCLVLr(x) ((x) & WMC_ALCLVL)
#define WMC_ALCLVLw(x) ((x) & WMC_ALCLVL)
/* WM8978_ALC_CONTROL3 (0x22) */
#define WM8978_ALCMODE (1 << 8)
#define WM8978_ALCDCY (0xf << 4)
#define WM8978_ALCATK (0xf << 0)
/* WMC_ALC_CONTROL3 (0x22) */
#define WMC_ALCMODE (1 << 8)
#define WMC_ALCDCY (0xf << 4)
#define WMC_ALCATK (0xf << 0)
/* WM8978_NOISE_GATE (0x23) */
#define WM8978_NGEN (1 << 3)
/* WMC_NOISE_GATE (0x23) */
#define WMC_NGEN (1 << 3)
/* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */
#define WM8978_NGTH (7 << 0)
#define WM8978_NGTHr(x) ((x) & WM8978_NGTH)
#define WM8978_NGTHw(x) ((x) & WM8978_NGTH)
#define WMC_NGTH (7 << 0)
#define WMC_NGTHr(x) ((x) & WMC_NGTH)
#define WMC_NGTHw(x) ((x) & WMC_NGTH)
/* WM8978_PLL_N (0x24) */
#define WM8978_PLL_PRESCALE (1 << 4)
#define WM8978_PLLN (0xf << 0)
#define WM8978_PLLNr(x) ((x) & WM8978_PLLN)
#define WM8978_PLLNw(x) ((x) & WM8978_PLLN)
/* WMC_PLL_N (0x24) */
#define WMC_PLL_PRESCALE (1 << 4)
#define WMC_PLLN (0xf << 0)
#define WMC_PLLNr(x) ((x) & WMC_PLLN)
#define WMC_PLLNw(x) ((x) & WMC_PLLN)
/* WM8978_PLL_K1 (0x25) */
#define WM8978_PLLK_23_18 (0x3f << 0)
#define WM8978_PLLK_23_18r(x) ((x) & WM8978_PLLK_23_18)
#define WM8978_PLLK_23_18w(x) ((x) & WM8978_PLLK_23_18)
/* WMC_PLL_K1 (0x25) */
#define WMC_PLLK_23_18 (0x3f << 0)
#define WMC_PLLK_23_18r(x) ((x) & WMC_PLLK_23_18)
#define WMC_PLLK_23_18w(x) ((x) & WMC_PLLK_23_18)
/* WM8978_PLL_K2 (0x26) */
#define WM8978_PLLK_17_9 (0x1ff << 0)
#define WM8978_PLLK_17_9r(x) ((x) & WM8978_PLLK_17_9)
#define WM8978_PLLK_17_9w(x) ((x) & WM8978_PLLK_17_9)
/* WMC_PLL_K2 (0x26) */
#define WMC_PLLK_17_9 (0x1ff << 0)
#define WMC_PLLK_17_9r(x) ((x) & WMC_PLLK_17_9)
#define WMC_PLLK_17_9w(x) ((x) & WMC_PLLK_17_9)
/* WM8978_PLL_K3 (0x27) */
#define WM8978_PLLK_8_0 (0x1ff << 0)
#define WM8978_PLLK_8_0r(x) ((x) & WM8978_PLLK_8_0)
#define WM8978_PLLK_8_0w(x) ((x) & WM8978_PLLK_8_0)
/* WMC_PLL_K3 (0x27) */
#define WMC_PLLK_8_0 (0x1ff << 0)
#define WMC_PLLK_8_0r(x) ((x) & WMC_PLLK_8_0)
#define WMC_PLLK_8_0w(x) ((x) & WMC_PLLK_8_0)
/* WM8978_3D_CONTROL (0x29) */
/* WMC_3D_CONTROL (0x29) */
/* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */
#define WM8978_DEPTH3D (0xf << 0)
#define WM8978_DEPTH3Dw(x) ((x) & WM8978_DEPTH3D)
#define WM8978_DEPTH3Dr(x) ((x) & WM8978_DEPTH3D)
#define WMC_DEPTH3D (0xf << 0)
#define WMC_DEPTH3Dw(x) ((x) & WMC_DEPTH3D)
#define WMC_DEPTH3Dr(x) ((x) & WMC_DEPTH3D)
/* WM8978_BEEP_CONTROL (0x2b) */
#define WM8978_MUTERPGA2INV (1 << 5)
#define WM8978_INVROUT2 (1 << 4)
/* WMC_BEEP_CONTROL (0x2b) */
#define WMC_MUTERPGA2INV (1 << 5)
#define WMC_INVROUT2 (1 << 4)
/* 000=-15dB, 001=-12dB...111=+6dB */
#define WM8978_BEEPVOL (7 << 1)
#define WM8978_BEEPVOLr(x) (((x) & WM8978_BEEPVOL) >> 1)
#define WM8978_BEEPVOLw(x) (((x) << 1) & WM8978_BEEPVOL)
#define WM8978_BEEPEN (1 << 0)
#define WMC_BEEPVOL (7 << 1)
#define WMC_BEEPVOLr(x) (((x) & WMC_BEEPVOL) >> 1)
#define WMC_BEEPVOLw(x) (((x) << 1) & WMC_BEEPVOL)
#define WMC_BEEPEN (1 << 0)
/* WM8978_INPUT_CTRL (0x2c) */
#define WM8978_MBVSEL (1 << 8)
#define WM8978_R2_2INPPGA (1 << 6)
#define WM8978_RIN2INPPGA (1 << 5)
#define WM8978_RIP2INPPGA (1 << 4)
#define WM8978_L2_2INPPGA (1 << 2)
#define WM8978_LIN2INPPGA (1 << 1)
#define WM8978_LIP2INPPGA (1 << 0)
/* WMC_INPUT_CTRL (0x2c) */
#define WMC_MBVSEL (1 << 8)
#define WMC_R2_2INPPGA (1 << 6)
#define WMC_RIN2INPPGA (1 << 5)
#define WMC_RIP2INPPGA (1 << 4)
#define WMC_L2_2INPPGA (1 << 2)
#define WMC_LIN2INPPGA (1 << 1)
#define WMC_LIP2INPPGA (1 << 0)
/* WM8978_LEFT_INP_PGA_GAIN_CTRL (0x2d) */
#define WM8978_INPPGAUPDATEL (1 << 8)
#define WM8978_NPPGAZCL (1 << 7)
#define WM8978_INPPGAMUTEL (1 << 6)
/* WMC_LEFT_INP_PGA_GAIN_CTRL (0x2d) */
/* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */
#define WM8978_INPPGAVOLL (0x3f << 0)
#define WM8978_INPPGAVOLLr(x) ((x) & WM8978_INPPGAVOLL)
#define WM8978_INPPGAVOLLw(x) ((x) & WM8978_INPPGAVOLL)
/* Uses WMC_AVOL* macros */
/* WM8978_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */
#define WM8978_INPPGAUPDATER (1 << 8)
#define WM8978_NPPGAZCR (1 << 7)
#define WM8978_INPPGAMUTER (1 << 6)
/* WMC_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */
/* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */
#define WM8978_INPPGAVOLR (0x3f << 0)
#define WM8978_INPPGAVOLRr(x) ((x) & WM8978_INPPGAVOLR)
#define WM8978_INPPGAVOLRw(x) ((x) & WM8978_INPPGAVOLR)
/* Uses WMC_AVOL* macros */
/* WM8978_LEFT_ADC_BOOST_CTRL (0x2f) */
#define WM8978_PGABOOSTL (1 << 8)
/* WMC_LEFT_ADC_BOOST_CTRL (0x2f) */
#define WMC_PGABOOSTL (1 << 8)
/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
#define WM8978_L2_2BOOSTVOL (7 << 4)
#define WM8978_L2_2BOOSTVOLr(x) ((x) & WM8978_L2_2_BOOSTVOL) >> 4)
#define WM8978_L2_2BOOSTVOLw(x) ((x) << 4) & WM8978_L2_2_BOOSTVOL)
#define WMC_L2_2BOOSTVOL (7 << 4)
#define WMC_L2_2BOOSTVOLr(x) ((x) & WMC_L2_2_BOOSTVOL) >> 4)
#define WMC_L2_2BOOSTVOLw(x) ((x) << 4) & WMC_L2_2_BOOSTVOL)
/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
#define WM8978_AUXL2BOOSTVOL (7 << 0)
#define WM8978_AUXL2BOOSTVOLr(x) ((x) & WM8978_AUXL2BOOSTVOL)
#define WM8978_AUXL2BOOSTVOLw(x) ((x) & WM8978_AUXL2BOOSTVOL)
#define WMC_AUXL2BOOSTVOL (7 << 0)
#define WMC_AUXL2BOOSTVOLr(x) ((x) & WMC_AUXL2BOOSTVOL)
#define WMC_AUXL2BOOSTVOLw(x) ((x) & WMC_AUXL2BOOSTVOL)
/* WM8978_RIGHT_ADC_BOOST_CTRL (0x30) */
#define WM8978_PGABOOSTR (1 << 8)
/* WMC_RIGHT_ADC_BOOST_CTRL (0x30) */
#define WMC_PGABOOSTR (1 << 8)
/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
#define WM8978_R2_2_BOOSTVOL (7 << 4)
#define WM8978_R2_2BOOSTVOLr(x) ((x) & WM8978_R2_2_BOOSTVOL) >> 4)
#define WM8978_R2_2BOOSTVOLw(x) ((x) << 4) & WM8978_R2_2_BOOSTVOL)
#define WMC_R2_2_BOOSTVOL (7 << 4)
#define WMC_R2_2BOOSTVOLr(x) ((x) & WMC_R2_2_BOOSTVOL) >> 4)
#define WMC_R2_2BOOSTVOLw(x) ((x) << 4) & WMC_R2_2_BOOSTVOL)
/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
#define WM8978_AUXR2BOOSTVOL (7 << 0)
#define WM8978_AUXR2BOOSTVOLr(x) ((x) & WM8978_AUXR2BOOSTVOL)
#define WM8978_AUXR2BOOSTVOLw(x) ((x) & WM8978_AUXR2BOOSTVOL)
#define WMC_AUXR2BOOSTVOL (7 << 0)
#define WMC_AUXR2BOOSTVOLr(x) ((x) & WMC_AUXR2BOOSTVOL)
#define WMC_AUXR2BOOSTVOLw(x) ((x) & WMC_AUXR2BOOSTVOL)
/* WM8978_OUTPUT_CTRL (0x31) */
#define WM8978_DACL2RMIX (1 << 6)
#define WM8978_DACR2LMIX (1 << 5)
#define WM8978_OUT4BOOST (1 << 4)
#define WM8978_OUT3BOOST (1 << 3)
#define WM8978_SPKBOOST (1 << 2)
#define WM8978_TSDEN (1 << 1)
#define WM8978_VROI (1 << 0)
/* WMC_OUTPUT_CTRL (0x31) */
#define WMC_DACL2RMIX (1 << 6)
#define WMC_DACR2LMIX (1 << 5)
#define WMC_OUT4BOOST (1 << 4)
#define WMC_OUT3BOOST (1 << 3)
#define WMC_SPKBOOST (1 << 2)
#define WMC_TSDEN (1 << 1)
#define WMC_VROI (1 << 0)
/* WM8978_LEFT_MIXER_CTRL (0x32) */
/* WMC_LEFT_MIXER_CTRL (0x32) */
/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
#define WM8978_AUXLMIXVOL (7 << 6)
#define WM8978_AUXLMIXVOLr(x) ((x) & WM8978_AUXLMIXVOL) >> 6)
#define WM8978_AUXLMIXVOLw(x) ((x) << 6) & WM8978_AUXLMIXVOL)
#define WM8978_AUXL2LMIX (1 << 5)
#define WMC_AUXLMIXVOL (7 << 6)
#define WMC_AUXLMIXVOLr(x) ((x) & WMC_AUXLMIXVOL) >> 6)
#define WMC_AUXLMIXVOLw(x) ((x) << 6) & WMC_AUXLMIXVOL)
#define WMC_AUXL2LMIX (1 << 5)
/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
#define WM8978_BYPLMIXVOL (7 << 2)
#define WM8978_BYPLMIXVOLr(x) ((x) & WM8978_BYPLMIXVOL) >> 2)
#define WM8978_BYPLMIXVOLw(x) ((x) << 2) & WM8978_BYPLMIXVOL)
#define WM8978_BYPL2LMIX (1 << 1)
#define WM8978_DACL2LMIX (1 << 0)
#define WMC_BYPLMIXVOL (7 << 2)
#define WMC_BYPLMIXVOLr(x) ((x) & WMC_BYPLMIXVOL) >> 2)
#define WMC_BYPLMIXVOLw(x) ((x) << 2) & WMC_BYPLMIXVOL)
#define WMC_BYPL2LMIX (1 << 1)
#define WMC_DACL2LMIX (1 << 0)
/* WM8978_RIGHT_MIXER_CTRL (0x33) */
/* WMC_RIGHT_MIXER_CTRL (0x33) */
/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
#define WM8978_AUXRMIXVOL (7 << 6)
#define WM8978_AUXRMIXVOLr(x) ((x) & WM8978_AUXRMIXVOL) >> 6)
#define WM8978_AUXRMIXVOLw(x) ((x) << 6) & WM8978_AUXRMIXVOL)
#define WM8978_AUXR2RMIX (1 << 5)
#define WMC_AUXRMIXVOL (7 << 6)
#define WMC_AUXRMIXVOLr(x) ((x) & WMC_AUXRMIXVOL) >> 6)
#define WMC_AUXRMIXVOLw(x) ((x) << 6) & WMC_AUXRMIXVOL)
#define WMC_AUXR2RMIX (1 << 5)
/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
#define WM8978_BYPRMIXVOL (7 << 2)
#define WM8978_BYPRMIXVOLr(x) ((x) & WM8978_BYPRMIXVOL) >> 2)
#define WM8978_BYPRMIXVOLw(x) ((x) << 2) & WM8978_BYPRMIXVOL)
#define WM8978_BYPR2RMIX (1 << 1)
#define WM8978_DACR2RMIX (1 << 0)
#define WMC_BYPRMIXVOL (7 << 2)
#define WMC_BYPRMIXVOLr(x) ((x) & WMC_BYPRMIXVOL) >> 2)
#define WMC_BYPRMIXVOLw(x) ((x) << 2) & WMC_BYPRMIXVOL)
#define WMC_BYPR2RMIX (1 << 1)
#define WMC_DACR2RMIX (1 << 0)
/* WM8978_LOUT1_HP_VOLUME_CTRL (0x34) */
#define WM8978_LHPVU (1 << 8)
#define WM8978_LOUT1ZC (1 << 7)
#define WM8978_LOUT1MUTE (1 << 6)
/* WMC_LOUT1_HP_VOLUME_CTRL (0x34) */
/* WMC_ROUT1_HP_VOLUME_CTRL (0x35) */
/* WMC_LOUT2_SPK_VOLUME_CTRL (0x36) */
/* WMC_ROUT2_SPK_VOLUME_CTRL (0x37) */
/* 000000=-57dB...111001=0dB...111111=+6dB */
#define WM8978_LOUT1VOL (0x3f << 0)
#define WM8978_LOUT1VOLr(x) ((x) & WM8978_LOUT1VOL)
#define WM8978_LOUT1VOLw(x) ((x) & WM8978_LOUT1VOL)
/* Uses WMC_AVOL* macros */
/* WM8978_ROUT1_HP_VOLUME_CTRL (0x35) */
#define WM8978_RHPVU (1 << 8)
#define WM8978_ROUT1ZC (1 << 7)
#define WM8978_ROUT1MUTE (1 << 6)
/* 000000=-57dB...111001=0dB...111111=+6dB */
#define WM8978_ROUT1VOL (0x3f << 0)
#define WM8978_ROUT1VOLr(x) ((x) & WM8978_ROUT1VOL)
#define WM8978_ROUT1VOLw(x) ((x) & WM8978_ROUT1VOL)
/* WMC_OUT3_MIXER_CTRL (0x38) */
#define WMC_OUT3MUTE (1 << 6)
#define WMC_OUT42OUT3 (1 << 3)
#define WMC_BYPL2OUT3 (1 << 2)
#define WMC_LMIX2OUT3 (1 << 1)
#define WMC_LDAC2OUT3 (1 << 0)
/* WM8978_LOUT2_SPK_VOLUME_CTRL (0x36) */
#define WM8978_LSPKVU (1 << 8)
#define WM8978_LOUT2ZC (1 << 7)
#define WM8978_LOUT2MUTE (1 << 6)
/* 000000=-57dB...111001=0dB...111111=+6dB */
#define WM8978_LOUT2VOL (0x3f << 0)
#define WM8978_LOUT2VOLr(x) ((x) & WM8978_LOUT2VOL)
#define WM8978_LOUT2VOLw(x) ((x) & WM8978_LOUT2VOL)
/* WM8978_ROUT2_SPK_VOLUME_CTRL (0x37) */
#define WM8978_RSPKVU (1 << 8)
#define WM8978_ROUT2ZC (1 << 7)
#define WM8978_ROUT2MUTE (1 << 6)
/* 000000=-57dB...111001=0dB...111111=+6dB */
#define WM8978_ROUT2VOL (0x3f << 0)
#define WM8978_ROUT2VOLr(x) ((x) & WM8978_ROUT2VOL)
#define WM8978_ROUT2VOLw(x) ((x) & WM8978_ROUT2VOL)
/* WM8978_OUT3_MIXER_CTRL (0x38) */
#define WM8978_OUT3MUTE (1 << 6)
#define WM8978_OUT42OUT3 (1 << 3)
#define WM8978_BYPL2OUT3 (1 << 2)
#define WM8978_LMIX2OUT3 (1 << 1)
#define WM8978_LDAC2OUT3 (1 << 0)
/* WM8978_OUT4_MONO_MIXER_CTRL (0x39) */
#define WM8978_OUT4MUTE (1 << 6)
#define WM8978_HALFSIG (1 << 5)
#define WM8978_LMIX2OUT4 (1 << 4)
#define WM8978_LDAC2OUT4 (1 << 3)
#define WM8978_BYPR2OUT4 (1 << 2)
#define WM8978_RMIX2OUT4 (1 << 1)
#define WM8978_RDAC2OUT4 (1 << 0)
/* WMC_OUT4_MONO_MIXER_CTRL (0x39) */
#define WMC_OUT4MUTE (1 << 6)
#define WMC_HALFSIG (1 << 5)
#define WMC_LMIX2OUT4 (1 << 4)
#define WMC_LDAC2OUT4 (1 << 3)
#define WMC_BYPR2OUT4 (1 << 2)
#define WMC_RMIX2OUT4 (1 << 1)
#define WMC_RDAC2OUT4 (1 << 0)
#endif /* _WM8978_H */

8
firmware/sound.c
View file

@ -308,7 +308,7 @@ static void set_prescaled_volume(void)
audiohw_set_lineout_vol(tenthdb2master(0), tenthdb2master(0));
#endif
#elif defined(HAVE_TLV320)
#elif defined(HAVE_TLV320) || defined(HAVE_WM8978)
audiohw_set_headphone_vol(tenthdb2master(l), tenthdb2master(r));
#endif
}
@ -333,7 +333,8 @@ void sound_set_volume(int value)
#elif (CONFIG_CODEC == MAS3507D) || defined HAVE_UDA1380 \
|| defined HAVE_WM8975 || defined HAVE_WM8758 || defined HAVE_WM8731 \
|| defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \
|| defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100)
|| defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100) \
|| defined(HAVE_WM8978)
current_volume = value * 10; /* tenth of dB */
set_prescaled_volume();
#elif CONFIG_CPU == PNX0101
@ -353,7 +354,8 @@ void sound_set_balance(int value)
#elif CONFIG_CODEC == MAS3507D || defined HAVE_UDA1380 \
|| defined HAVE_WM8975 || defined HAVE_WM8758 || defined HAVE_WM8731 \
|| defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \
|| defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100)
|| defined(HAVE_AS3514) || defined(HAVE_WM8985) || defined(HAVE_TSC2100) \
|| defined(HAVE_WM8978)
current_balance = value * VOLUME_RANGE / 100; /* tenth of dB */
set_prescaled_volume();
#elif CONFIG_CPU == PNX0101

119
firmware/target/arm/imx31/debug-imx31.c
View file

@ -27,10 +27,129 @@
#include "mc13783.h"
#include "adc.h"
#define CONFIG_CLK32_FREQ 32768
#define CONFIG_HCLK_FREQ 27000000
/* Return PLL frequency in HZ */
static unsigned int decode_pll(unsigned int reg,
unsigned int infreq)
{
uint64_t mfi = (reg >> 10) & 0xf;
uint64_t mfn = reg & 0x3ff;
uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
uint64_t pd = ((reg >> 26) & 0xf) + 1;
mfi = mfi <= 5 ? 5 : mfi;
return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
}
/* Get the PLL reference clock frequency */
static unsigned int get_pll_ref_clk_freq(void)
{
if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1))
return CONFIG_CLK32_FREQ * 1024;
else
return CONFIG_HCLK_FREQ;
}
bool __dbg_hw_info(void)
{
char buf[50];
int line;
unsigned int pllref;
unsigned int mcu_pllfreq, ser_pllfreq, usb_pllfreq;
uint32_t mpctl, spctl, upctl;
unsigned int freq;
uint32_t regval;
lcd_setmargins(0, 0);
lcd_clear_display();
lcd_setfont(FONT_SYSFIXED);
while (1)
{
line = 0;
mpctl = CLKCTL_MPCTL;
spctl = CLKCTL_SPCTL;
upctl = CLKCTL_UPCTL;
pllref = get_pll_ref_clk_freq();
mcu_pllfreq = decode_pll(mpctl, pllref);
ser_pllfreq = decode_pll(spctl, pllref);
usb_pllfreq = decode_pll(upctl, pllref);
snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref);
lcd_puts(0, line++, buf); line++;
/* MCU clock domain */
snprintf(buf, sizeof (buf), "MPCTL: %08lX", mpctl);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq);
lcd_puts(0, line++, buf); line++;
regval = CLKCTL_PDR0;
snprintf(buf, sizeof (buf), " PDR0: %08lX", regval);
lcd_puts(0, line++, buf);
freq = mcu_pllfreq / (((regval & 0x7) + 1));
snprintf(buf, sizeof (buf), " mcu_clk: %u", freq);
lcd_puts(0, line++, buf);
freq = mcu_pllfreq / (((regval >> 11) & 0x7) + 1);
snprintf(buf, sizeof (buf), " hsp_clk: %u", freq);
lcd_puts(0, line++, buf);
freq = mcu_pllfreq / (((regval >> 3) & 0x7) + 1);
snprintf(buf, sizeof (buf), " hclk_clk: %u", freq);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof (buf), " ipg_clk: %u",
freq / (unsigned)(((regval >> 6) & 0x3) + 1));
lcd_puts(0, line++, buf);
snprintf(buf, sizeof (buf), " nfc_clk: %u",
freq / (unsigned)(((regval >> 8) & 0x7) + 1));
lcd_puts(0, line++, buf);
line++;
/* Serial clock domain */
snprintf(buf, sizeof (buf), "SPCTL: %08lX", spctl);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof (buf), " spl_dpdgck_clk: %u", ser_pllfreq);
lcd_puts(0, line++, buf);
line++;
/* USB clock domain */
snprintf(buf, sizeof (buf), "UPCTL: %08lX", upctl);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq);
lcd_puts(0, line++, buf); line++;
regval = CLKCTL_PDR1;
snprintf(buf, sizeof (buf), " PDR1: %08lX", regval);
lcd_puts(0, line++, buf);
freq = usb_pllfreq /
((((regval >> 30) & 0x3) + 1) * (((regval >> 27) & 0x7) + 1));
snprintf(buf, sizeof (buf), " usb_clk: %u", freq);
lcd_puts(0, line++, buf);
freq = usb_pllfreq / (((CLKCTL_PDR0 >> 16) & 0x1f) + 1);
snprintf(buf, sizeof (buf), " ipg_per_baud: %u", freq);
lcd_puts(0, line++, buf);
lcd_update();
if (button_get(true) == (DEBUG_CANCEL|BUTTON_REL))
return false;
}
}
bool __dbg_ports(void)
{

228
firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
View file

@ -7,7 +7,7 @@
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2006 by Michael Sevakis
* Copyright (C) 2008 by Michael Sevakis
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
@ -19,69 +19,256 @@
#include <stdlib.h>
#include "system.h"
#include "kernel.h"
#include "logf.h"
#include "audio.h"
#include "sound.h"
#include "file.h"
#include "mmu-imx31.h"
#include "avic-imx31.h"
#include "clkctl-imx31.h"
#if 0
static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
#endif
/* This isn't DMA-based at the moment and is handled like Portal Player but
* will suffice for starters. */
struct dma_data
{
uint16_t *p;
size_t size;
int locked;
int state;
};
static unsigned long pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
static struct dma_data dma_play_data =
{
/* Initialize to a locked, stopped state */
.p = NULL,
.size = 0,
.locked = 0,
.state = 0
};
void pcm_play_lock(void)
{
if (++dma_play_data.locked == 1)
{
/* Atomically disable transmit interrupt */
imx31_regmod32(&SSI_SIER1, 0, SSI_SIER_TIE);
}
}
void pcm_play_unlock(void)
{
if (--dma_play_data.locked == 0 && dma_play_data.state != 0)
{
/* Atomically enable transmit interrupt */
imx31_regmod32(&SSI_SIER1, SSI_SIER_TIE, SSI_SIER_TIE);
}
}
#if 0
static void _pcm_apply_settings(void)
{
if (pcm_freq != pcm_curr_sampr)
{
pcm_curr_sampr = pcm_freq;
// TODO: audiohw_set_frequency(sr_ctrl);
}
}
static void __attribute__((interrupt("IRQ"))) SSI1_HANDLER(void)
{
register pcm_more_callback_type get_more;
do
{
while (dma_play_data.size > 0)
{
if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6)
{
return;
}
SSI_STX0_1 = *dma_play_data.p++;
SSI_STX0_1 = *dma_play_data.p++;
dma_play_data.size -= 4;
}
/* p is empty, get some more data */
get_more = pcm_callback_for_more;
if (get_more)
{
get_more((unsigned char **)&dma_play_data.p,
&dma_play_data.size);
}
}
while (dma_play_data.size > 0);
/* No more data, so disable the FIFO/interrupt */
pcm_play_dma_stop();
pcm_play_dma_stopped_callback();
}
#endif
void pcm_apply_settings(void)
{
int oldstatus = disable_fiq_save();
_pcm_apply_settings();
restore_fiq(oldstatus);
}
void pcm_play_dma_init(void)
{
imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL);
imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL);
/* Reset & disable SSIs */
SSI_SCR2 &= ~SSI_SCR_SSIEN;
SSI_SCR1 &= ~SSI_SCR_SSIEN;
SSI_SIER1 = SSI_SIER_TFE0;
SSI_SIER2 = 0;
/* Set up audio mux */
/* Port 1 (internally connected to SSI1)
* All clocking is output sourced from port 4 */
AUDMUX_PTCR1 = AUDMUX_PTCR_TFS_DIR | AUDMUX_PTCR_TFSEL_PORT4 |
AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT4 |
AUDMUX_PTCR_RFSDIR | AUDMUX_PTCR_RFSSEL_PORT4 |
AUDMUX_PTCR_RCLKDIR | AUDMUX_PTCR_RCSEL_PORT4 |
AUDMUX_PTCR_SYN;
/* Receive data from port 4 */
AUDMUX_PDCR1 = AUDMUX_PDCR_RXDSEL_PORT4;
/* All clock lines are inputs sourced from the master mode codec and
* sent back to SSI1 through port 1 */
AUDMUX_PTCR4 = AUDMUX_PTCR_SYN;
/* Receive data from port 1 */
AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT1;
/* Port 2 (internally connected to SSI2) routes clocking to port 5 to
* provide MCLK to the codec */
/* All port 2 clocks are inputs taken from SSI2 */
AUDMUX_PTCR2 = 0;
AUDMUX_PDCR2 = 0;
/* Port 5 outputs TCLK sourced from port 2 */
AUDMUX_PTCR5 = AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT2;
AUDMUX_PDCR5 = 0;
/* Setup SSIs */
/* SSI1 - interface for all I2S data */
SSI_SCR1 = SSI_SCR_SYN | SSI_SCR_I2S_MODE_SLAVE;
SSI_STCR1 = SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI |
SSI_STCR_TEFS | SSI_STCR_TFEN0;
/* 16 bits per word, 2 words per frame */
SSI_STCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
SSI_STRCCR_PMw(4-1);
SSI_STMSK1 = 0;
/* Receive */
SSI_SRCR1 = SSI_SRCR_RXBIT0 | SSI_SRCR_RSCKP | SSI_SRCR_RFSI |
SSI_SRCR_REFS | SSI_SRCR_RFEN0;
/* 16 bits per word, 2 words per frame */
SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
SSI_STRCCR_PMw(4-1);
/* Receive high watermark - 6 samples in FIFO
* Transmit low watermark - 2 samples in FIFO */
SSI_SFCSR1 = SSI_SFCSR_RFWM1w(8) | SSI_SFCSR_TFWM1w(1) |
SSI_SFCSR_RFWM0w(6) | SSI_SFCSR_TFWM0w(2);
SSI_SRMSK1 = 0;
/* SSI2 - provides MCLK only */
SSI_SCR2 = 0;
SSI_SRCR2 = 0;
SSI_STCR2 = SSI_STCR_TXDIR;
SSI_STCCR2 = SSI_STRCCR_PMw(0);
/* Enable SSIs */
SSI_SCR2 |= SSI_SCR_SSIEN;
audiohw_init();
}
void pcm_postinit(void)
{
audiohw_postinit();
avic_enable_int(SSI1, IRQ, 8, SSI1_HANDLER);
}
#if 0
/* Connect the DMA and start filling the FIFO */
static void play_start_pcm(void)
{
/* Stop transmission (if in progress) */
SSI_SCR1 &= ~SSI_SCR_TE;
/* Apply new settings */
_pcm_apply_settings();
/* Enable interrupt on unlock */
dma_play_data.state = 1;
/* Fill the FIFO or start when data is used up */
while (1)
{
if (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 6 || dma_play_data.size == 0)
{
SSI_SCR1 |= (SSI_SCR_TE | SSI_SCR_SSIEN); /* Start transmitting */
return;
}
SSI_STX0_1 = *dma_play_data.p++;
SSI_STX0_1 = *dma_play_data.p++;
dma_play_data.size -= 4;
}
}
/* Disconnect the DMA and wait for the FIFO to clear */
static void play_stop_pcm(void)
{
/* Disable interrupt */
SSI_SIER1 &= ~SSI_SIER_TIE;
/* Wait for FIFO to empty */
while (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 0);
/* Disable transmission */
SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN);
/* Do not enable interrupt on unlock */
dma_play_data.state = 0;
}
#endif
void pcm_play_dma_start(const void *addr, size_t size)
{
(void)addr;
(void)size;
dma_play_data.p = (void *)(((uintptr_t)addr + 3) & ~3);
dma_play_data.size = (size & ~3);
play_start_pcm();
}
void pcm_play_dma_stop(void)
{
play_stop_pcm();
dma_play_data.size = 0;
}
void pcm_play_dma_pause(bool pause)
{
(void)pause;
if (pause)
{
play_stop_pcm();
}
else
{
uint32_t addr = (uint32_t)dma_play_data.p;
dma_play_data.p = (void *)((addr + 2) & ~3);
dma_play_data.size &= ~3;
play_start_pcm();
}
}
/* Set the pcm frequency hardware will use when play is next started or
@ -89,20 +276,23 @@ void pcm_play_dma_pause(bool pause)
hardware here but simply cache it. */
void pcm_set_frequency(unsigned int frequency)
{
/* TODO */
(void)frequency;
}
/* Return the number of bytes waiting - full L-R sample pairs only */
size_t pcm_get_bytes_waiting(void)
{
return 0;
return dma_play_data.size & ~3;
}
/* Return a pointer to the samples and the number of them in *count */
const void * pcm_play_dma_get_peak_buffer(int *count)
{
(void)count;
return NULL;
uint32_t addr = (uint32_t)dma_play_data.p;
size_t cnt = dma_play_data.size;
*count = cnt >> 2;
return (void *)((addr + 2) & ~3);
}
/* Any recording functionality should be implemented similarly */

10
firmware/target/arm/imx31/gigabeat-s/system-imx31.c
View file

@ -27,6 +27,16 @@ void system_init(void)
gpio_init();
}
void imx31_regmod32(volatile uint32_t *reg_p, uint32_t mask, uint32_t value)
{
value &= mask;
mask = ~mask;
int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
*reg_p = (*reg_p & mask) | value;
restore_interrupt(oldlevel);
}
#ifdef BOOTLOADER
void system_prepare_fw_start(void)
{

5
firmware/target/arm/imx31/gigabeat-s/system-target.h
View file

@ -24,16 +24,21 @@
#define CPUFREQ_NORMAL 532000000
#if 0
static inline void udelay(unsigned int usecs)
{
volatile signed int stop = EPITCNT1 - usecs;
while ((signed int)EPITCNT1 > stop);
}
#endif
void system_prepare_fw_start(void);
void tick_stop(void);
void kernel_device_init(void);
void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value,
uint32_t mask);
#define KDEV_INIT
#define HAVE_INVALIDATE_ICACHE

34
firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
View file

@ -9,12 +9,7 @@
*
* Gigabeat S specific code for the WM8978 codec
*
* Based on code from the ipodlinux project - http://ipodlinux.org/
* Adapted for Rockbox in December 2005
*
* Original file: linux/arch/armnommu/mach-ipod/audio.c
*
* Copyright (c) 2003-2005 Bernard Leach (leachbj@bouncycastle.org)
* Copyright (C) 2008 Michael Sevakis
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
@ -23,7 +18,8 @@
* KIND, either express or implied.
*
****************************************************************************/
#include "cpu.h"
#include "config.h"
#include "system.h"
#include "kernel.h"
#include "sound.h"
#include "i2c-imx31.h"
@ -37,15 +33,33 @@ static struct i2c_node wm8978_i2c_node =
.ifdr = I2C_IFDR_DIV192, /* 66MHz/.4MHz = 165, closest = 192 = 343750Hz */
/* Just hard-code for now - scaling may require
* updating */
.addr = WM8978_I2C_ADDR,
.addr = WMC_I2C_ADDR,
};
void audiohw_init(void)
{
/* USB PLL = 338.688MHz, /30 = 11.2896MHz = 256Fs */
imx31_regmod32(&CLKCTL_PDR1, PDR1_SSI1_PODF | PDR1_SSI2_PODF,
PDR1_SSI1_PODFw(64-1) | PDR1_SSI2_PODFw(5-1));
imx31_regmod32(&CLKCTL_PDR1, PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF,
PDR1_SSI1_PRE_PODFw(4-1) | PDR1_SSI2_PRE_PODFw(1-1));
i2c_enable_node(&wm8978_i2c_node, true);
GPIO3_DR |= (1 << 21); /* Turn on analogue LDO */
sleep(HZ/10); /* Wait for things to stabilize */
audiohw_preinit();
GPIO3_DR |= (1 << 21); /* Turn on analogue LDO */
}
void audiohw_enable_headphone_jack(bool enable)
{
if (enable)
{
GPIO3_DR |= (1 << 22); /* Turn on headphone jack output */
}
else
{
GPIO3_DR &= ~(1 << 22); /* Turn off headphone jack output */
}
}
void wmcodec_write(int reg, int data)