Add some CACHEALIGN_* macros and a helper function to assist in aligning data and buffers on PortalPlayer processors to cache line boundaries. They're noops when PROC_NEED_CACHEALIGN isn't defined. Go safe and increase the value to 32 since I'm not sure yet if 16 is sufficient - changing that is a one-liner. Add helper to plugin API which will be needed shortly.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15523 a1c6a512-1295-4272-9138-f99709370657

firmware/target/arm/sandisk/sansa-e200/lcd-e200.c

@@ -109,9 +109,9 @@ static unsigned short r_drv_output_control  = R_DRV_OUTPUT_CONTROL_NORMAL;
 /* We don't know how to receive a DMA finished signal from the LCD controller
  * To avoid problems with flickering, we double-buffer the framebuffer and turn
  * off DMA while updates are taking place
- * Same alignment as in lcd-16bit.c and cache interference free */
+ * At least the alignment as in lcd-16bit.c and cache interference free */
 static fb_data lcd_driver_framebuffer[LCD_FBHEIGHT][LCD_FBWIDTH]
-    __attribute__((aligned(16)));
+    CACHEALIGN_AT_LEAST_ATTR(16);
 
 #ifdef BOOTLOADER
 static void lcd_init_gpio(void)

firmware/target/arm/system-target.h

@@ -94,11 +94,17 @@ static inline unsigned int processor_id(void)
 #define UNCACHED_ADDR(a) (a)
 #else
 #define UNCACHED_ADDR(a) \
-    ((typeof (a))((uintptr_t)(a) + 0x10000000))
+    ((typeof (a))((uintptr_t)(a) | 0x10000000))
 #endif
 
 #ifdef CPU_PP502x
 
+/* Certain data needs to be out of the way of cache line interference
+ * such as data for COP use or for use with UNCACHED_ADDR */
+#define PROC_NEEDS_CACHEALIGN
+#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
+
+/** cache functions **/
 #ifndef BOOTLOADER
 #define CACHE_FUNCTIONS_AS_CALL