forked from len0rd/rockbox
Enable tick IRQs on TCC780x. The main menu is now working on the D2.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16749 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rob Purchase
parent
f061ba4ebb
commit
4dc2d8ddba
6 changed files with 162 additions and 88 deletions
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@ -121,6 +121,52 @@ copied_start:
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msr cpsr, r0
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ldr sp, =stackend
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/* Enable MMU & caches. At present this is just doing what the OF does.
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Ensure TCMs are enabled before copying the exception vectors to 0x0. */
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mov r1, #0xf7000000 /* Virtual MMU Table base */
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ldr r0, =0x1fe0c /* Region 0: 0x00000000-0xffffffff (4Gb) */
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str r0, [r1] /* AP: 3 EN: 1 DO: 0 CACHE_ALL */
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ldr r0, =0x2801ae24 /* Region 1: 0x28000000-0x2fffffff (128Mb) */
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str r0, [r1,#4] /* AP: 3 EN: 1 DO: 1 BUFFERED */
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ldr r0, =0x13e44 /* Region 2: 0x00000000-0x000fffff (1Mb) */
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str r0, [r1,#8] /* AP: 3 EN: 1 DO: 2 BUFFERED */
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ldr r0, =0x4001ce60 /* Region 3: 0x40000000-0x5fffffff (512Mb) */
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str r0, [r1,#0xc] /* AP: 3 EN: 1 DO: 3 CACHE_NONE */
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ldr r0, =0x6001be80 /* Region 4: 0x60000000-0x6fffffff (256Mb) */
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str r0, [r1,#0x10] /* AP: 3 EN: 1 DO: 4 CACHE_NONE */
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ldr r0, =0x3801aea4 /* Region 5: 0x38000000-0x3fffffff (128Mb) */
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str r0, [r1,#0x14] /* AP: 3 EN: 1 DO: 5 BUFFERED */
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ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */
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str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */
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ldr r0, =0x1001aee0 /* Region 7: 0x10000000-0x17ffffff (128Mb) */
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str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_NONE */
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add r1, r1, #0x8000
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mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */
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ldr r0, =0x55555555
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mcr p15, 0, r0, c3, c0, 0 /* Domain access d0-d15 = 'client' */
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ldr r0, =0xa0000011
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mcr p15, 0, r0, c9, c1, 0 /* Data TCM: 0xA0000000-0xA00001fff (8Kb) */
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mov r0, #0xd
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mcr p15, 0, r0, c9, c1, 1 /* Instr. TCM: 0x00000000-0x00000fff (4Kb) */
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 /* Invalidate Icache */
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ldr r2, =0x5507d
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mcr p15, 0, r2, c1, c0, 0 /* Enable MMU, I & D caches */
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mcr p15, 0, r0, c7, c6, 0 /* Invalidate Dcache */
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mcr p15, 0, r1, c8, c7, 0 /* Invalidate TLB */
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#if !defined(BOOTLOADER) && !defined(STUB)
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@ -193,43 +239,6 @@ copied_start:
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strhi r4, [r2], #4
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bhi 1b
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/*
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Enable cache & TCM regions
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TODO: This is just doing what the OF does at present. It needs to be
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better understood and moved out to a separate MMU functions package.
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*/
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ldr r1, =0x1fe0c
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mov r0, #0xf7000000
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str r1, [r0]
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ldr r1, =0x2801ae24
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str r1, [r0,#4]
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ldr r1, =0x13e44
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str r1, [r0,#8]
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ldr r1, =0x4001ce60
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str r1, [r0,#0xc]
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ldr r1, =0x6001be80
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str r1, [r0,#0x10]
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ldr r1, =0x3801aea4
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str r1, [r0,#0x14]
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ldr r1, =0x8001eec0
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str r1, [r0,#0x18]
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ldr r1, =0x1001aee0
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str r1, [r0,#0x1c]
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add r1, r0, #0x8000 /* r1 now = 0xf7008000 */
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ldr r0, =0xa0000011
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ldr r2, =0x5507d
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mcr p15, 0, r0,c9,c1 /* data tcm region (enabled; 8kb; 0xa0000000) */
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mov r0, #0xd
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mcr p15, 0, r0,c9,c1, 1 /* inst tcm region (enabled, 4kb, 0x00000000) */
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ldr r0, =0x55555555
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mcr p15, 0, r1,c2,c0 /* translation table base register = 0xf7008000 */
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mcr p15, 0, r0,c3,c0 /* domain access d0-d15 = 'client' */
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mov r0, #0
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mcr p15, 0, r0,c7,c5 /* invalidate icache */
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mcr p15, 0, r2,c1,c0 /* enable mmu, i & d caches */
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mcr p15, 0, r0,c7,c6 /* invalidate dcache */
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mcr p15, 0, r1,c8,c7 /* invalidate tlb */
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bl main
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/* main() should never return */
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@ -36,8 +36,8 @@ void tick_start(unsigned int interval_in_ms)
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TCFG0 = (1<<8) | (0<<4) | (1<<3) | 1;
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/* Unmask timer IRQ */
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MIRQ &= ~TIMER_IRQ_MASK;
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IEN |= TIMER0_IRQ_MASK;
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}
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/* NB: Since the 7801 has a single timer IRQ, the tick tasks are dispatched
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as part of the central timer IRQ processing in timer-tcc780x.c */
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/* NB: Since we are using a single timer IRQ, tick tasks are dispatched as
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part of the central timer IRQ processing in timer-tcc780x.c */
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@ -33,49 +33,86 @@ default_interrupt(EXT0);
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default_interrupt(EXT1);
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default_interrupt(EXT2);
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default_interrupt(EXT3);
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default_interrupt(IRQ4);
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default_interrupt(IRQ5);
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default_interrupt(TIMER);
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default_interrupt(IRQ7);
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default_interrupt(IRQ8);
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default_interrupt(IRQ9);
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default_interrupt(IRQ10);
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default_interrupt(IRQ11);
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default_interrupt(IRQ12);
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default_interrupt(IRQ13);
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default_interrupt(RTC);
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default_interrupt(GPSB0);
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default_interrupt(TIMER0);
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default_interrupt(TIMER1);
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default_interrupt(SCORE);
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default_interrupt(SPDTX);
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default_interrupt(VIDEO);
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default_interrupt(GSIO);
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default_interrupt(SCALER);
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default_interrupt(I2C);
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default_interrupt(DAI_RX);
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default_interrupt(DAI_TX);
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default_interrupt(IRQ16);
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default_interrupt(IRQ17);
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default_interrupt(IRQ18);
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default_interrupt(IRQ19);
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default_interrupt(IRQ20);
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default_interrupt(IRQ21);
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default_interrupt(IRQ22);
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default_interrupt(IRQ23);
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default_interrupt(IRQ24);
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default_interrupt(IRQ25);
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default_interrupt(IRQ26);
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default_interrupt(IRQ27);
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default_interrupt(IRQ28);
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default_interrupt(IRQ29);
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default_interrupt(IRQ30);
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default_interrupt(IRQ31);
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default_interrupt(CDRX);
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default_interrupt(HPI);
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default_interrupt(UART0);
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default_interrupt(UART1);
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default_interrupt(G2D);
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default_interrupt(USB_DEVICE);
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default_interrupt(USB_HOST);
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default_interrupt(DMA);
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default_interrupt(HDD);
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default_interrupt(MSTICK);
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default_interrupt(NFC);
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default_interrupt(SDMMC);
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default_interrupt(CAM);
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default_interrupt(LCD);
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default_interrupt(ADC);
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default_interrupt(GPSB1);
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/* TODO: Establish IRQ priorities (0 = highest priority) */
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static const char irqpriority[] =
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{
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0, /* EXT0 */
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1, /* EXT1 */
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2, /* EXT2 */
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3, /* EXT3 */
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4, /* RTC */
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5, /* GPSB0 */
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6, /* TIMER0 */
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7, /* TIMER1 */
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8, /* SCORE */
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9, /* SPDTX */
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10, /* VIDEO */
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11, /* GSIO */
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12, /* SCALER */
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13, /* I2C */
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14, /* DAI_RX */
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15, /* DAI_TX */
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16, /* CDRX */
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17, /* HPI */
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18, /* UART0 */
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19, /* UART1 */
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20, /* G2D */
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21, /* USB_DEVICE */
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22, /* USB_HOST */
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23, /* DMA */
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24, /* HDD */
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25, /* MSTICK */
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26, /* NFC */
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27, /* SDMMC */
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28, /* CAM */
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29, /* LCD */
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30, /* ADC */
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31, /* GPSB */
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};
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static void (* const irqvector[])(void) =
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{
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EXT0,EXT1,EXT2,EXT3,IRQ4,IRQ5,TIMER,IRQ7,
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IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,DAI_RX,DAI_TX,
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IRQ16,IRQ17,IRQ18,IRQ19,IRQ20,IRQ21,IRQ22,IRQ23,
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IRQ24,IRQ25,IRQ26,IRQ27,IRQ28,IRQ29,IRQ30,IRQ31
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EXT0,EXT1,EXT2,EXT3,RTC,GPSB0,TIMER0,TIMER1,
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SCORE,SPDTX,VIDEO,GSIO,SCALER,I2C,DAI_RX,DAI_TX,
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CDRX,HPI,UART0,UART1,G2D,USB_DEVICE,USB_HOST,DMA,
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HDD,MSTICK,NFC,SDMMC,CAM,LCD,ADC,GPSB1
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};
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static const char * const irqname[] =
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{
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"EXT0","EXT1","EXT2","EXT3","IRQ4","IRQ5","TIMER","IRQ7",
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"IRQ8","IRQ9","IRQ10","IRQ11","IRQ12","IRQ13","DAI_RX","DAI_TX",
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"IRQ16","IRQ17","IRQ18","IRQ19","IRQ20","IRQ21","IRQ22","IRQ23",
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"IRQ24","IRQ25","IRQ26","IRQ27","IRQ28","IRQ29","IRQ30","IRQ31"
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"EXT0","EXT1","EXT2","EXT3","RTC","GPSB0","TIMER0","TIMER1",
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"SCORE","SPDTX","VIDEO","GSIO","SCALER","I2C","DAI_RX","DAI_TX",
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"CDRX","HPI","UART0","UART1","G2D","USB_DEVICE","USB_HOST","DMA",
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"HDD","MSTICK","NFC","SDMMC","CAM","LCD","ADC","GPSB1"
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};
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static void UIRQ(void)
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@ -92,17 +129,23 @@ void irq_handler(void)
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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irqvector[VNIRQ]();
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int irq_no = VNIRQ; /* Read clears the corresponding IRQ status */
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if ((irq_no & (1<<31)) == 0) /* Ensure invalid flag is not set */
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{
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irqvector[irq_no]();
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}
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from FIQ */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_handler(void)
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{
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asm volatile (
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"sub lr, lr, #4 \r\n"
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"movs lr,pc \r\n"
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"subs pc, lr, #4 \r\n"
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);
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}
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#endif /* !defined(BOOTLOADER) */
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@ -231,15 +274,36 @@ static void clock_init(void)
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#ifdef COWON_D2
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void system_init(void)
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{
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int i;
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MBCFG = 0x19;
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if (TCC780_VER == 0)
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ECFG0 = 0x309;
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else
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ECFG0 = 0x30d;
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/* mask all interrupts */
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MIRQ = -1;
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IEN = 0;
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#if !defined(BOOTLOADER)
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IRQSEL = -1; /* set all interrupts to be IRQs not FIQs */
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POL = 0x200108; /* IRQs 3,8,21 active low (as OF) */
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MODE = 0x20ce07c0; /* IRQs 6-10,17-19,22-23,29 level-triggered (as OF) */
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VCTRL |= (1<<31); /* Reading from VNIRQ clears that interrupt */
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/* Write IRQ priority registers using ints - a freeze occurs otherwise */
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for (i = 0; i < 7; i++)
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{
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IRQ_PRIORITY_TABLE[i] = ((int*)irqpriority)[i];
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}
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ALLMASK = 3; /* Global FIQ/IRQ unmask */
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#endif /* !defined(BOOTLOADER) */
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gpio_init();
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clock_init();
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@ -52,7 +52,7 @@ void __timer_unregister(void)
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extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
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void TIMER(void)
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void TIMER0(void)
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{
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if (TIREQ & TF0) /* Timer0 reached ref value */
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{
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@ -77,6 +77,4 @@ void TIMER(void)
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{
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/* dispatch timer */
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}
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CREQ |= TIMER_IRQ_MASK; /* clear IRQ */
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}
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