forked from len0rd/rockbox
imx233: rewrite i2c driver
The new driver provides several new features: - asynchronous transfer - transactions (several transfers executed at once) - queueing The style still provides the legacy interface. Change-Id: I6d8ecc89d1f7057847c9b2dc69b76cd45c9c8407
This commit is contained in:
Amaury Pouly
Gerrit Rockbox
parent
615c638c7d
commit
4d42e3685c
3 changed files with 356 additions and 78 deletions
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@ -24,7 +24,7 @@
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#include "fmradio-imx233.h"
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#include "fmradio-target.h"
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#include "pinctrl-imx233.h"
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#include "i2c.h"
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#include "i2c-imx233.h"
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#include "generic_i2c.h"
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#ifndef IMX233_FMRADIO_I2C
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@ -45,6 +45,166 @@
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* are cache aligned and will copy back the data to user buffers at the end.
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* The I2C_BUFFER_SIZE define controls the size of the buffer. All transfers
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* should probably fit within 512 bytes.
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*
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* On top of this, transfers are queued using the 'next' field of imx233_i2c_xfer_t.
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* Each time a transfer is programmed, it is translated to dma transfers using
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* the dma API.
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*/
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/**
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* Internal DMA API to build the transfer.
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* NOTE the api does not perform any locking, it is up to the caller to ensure
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* that there only one transfer beint built at any time.
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*/
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/* start building a transfer */
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static void imx233_i2c_begin(void);
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/* add a stage
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* NOTE for transmit, the data is copied to a buffer so the buffer can be freed
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* afer this function return. For receive, buffer must exists until transfer is
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* complete. This function assumes any receive transfer is final (master will
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* send NAK). */
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static void imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop);
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/* end building a transfer and start the transfer */
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static void imx233_i2c_kick(void);
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/* abort transfer (will call imx233_i2c_transfer_complete) */
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static void imx233_i2c_abort(void);
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/* set speed */
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static void imx233_i2c_set_speed(bool fast_mode);
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/* callback function when transfer is finished */
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static void imx233_i2c_transfer_complete(enum imx233_i2c_error_t status);
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/**
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* Advanced API
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*/
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/* NOTE these variables are not marked as volatile because all functions
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* do all operation with IRQ disabled, so they won't change their value
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* in the middle of a function */
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static struct imx233_i2c_xfer_t *i2c_head; /* pointer to the current transfer */
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static struct imx233_i2c_xfer_t *i2c_tail; /* pointer to the last transfer */
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static struct timeout i2c_tmo; /* timeout */
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/* timeout callback */
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static int imx233_i2c_timeout(struct timeout *tmo);
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/* called in IRQ context or with IRQ disabled */
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static void imx233_i2c_start(void)
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{
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uint8_t addr_wr = i2c_head->dev_addr;
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uint8_t addr_rd = i2c_head->dev_addr | 1;
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/* translate transfer using DMA API */
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imx233_i2c_set_speed(i2c_head->fast_mode);
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imx233_i2c_begin();
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if(i2c_head->mode == I2C_WRITE)
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{
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/* START + addr */
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imx233_i2c_add(true, true, &addr_wr, 1, false);
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/* data + stop if no second stage */
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imx233_i2c_add(false, true, i2c_head->data[0], i2c_head->count[0], i2c_head->count[1] == 0);
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/* (if second stage) data + stop */
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if(i2c_head->count[1] > 0)
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imx233_i2c_add(false, true, i2c_head->data[1], i2c_head->count[1], true);
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}
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else /* I2C_READ */
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{
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/* (if write stage) */
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if(i2c_head->count[0] > 0)
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{
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/* START + addr */
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imx233_i2c_add(true, true, &addr_wr, 1, false);
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/* data */
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imx233_i2c_add(false, true, i2c_head->data[0], i2c_head->count[0], false);
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}
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/* START + addr */
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imx233_i2c_add(true, true, &addr_rd, 1, false);
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/* read data + stop */
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imx233_i2c_add(false, false, i2c_head->data[1], i2c_head->count[1], true);
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}
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/* kick transfer */
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imx233_i2c_kick();
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/* setup timer for timeout */
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if(i2c_head->tmo_ms > 0)
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timeout_register(&i2c_tmo, imx233_i2c_timeout, i2c_head->tmo_ms * HZ / 1000, 0);
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}
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/* unqueue head and notify completion, called with IRQ disabled */
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static void imx233_i2c_unqueue_head(enum imx233_i2c_error_t status)
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{
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/* notify */
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if(i2c_head->callback)
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i2c_head->callback(i2c_head, status);
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/* unqueue */
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i2c_head = i2c_head->next;
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}
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/* callback function when transfer is finished, called with IRQ disabled */
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static void imx233_i2c_transfer_complete(enum imx233_i2c_error_t status)
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{
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/* cancel timeout
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* NOTE because IRQ are disabled, the timeout callback will not be called
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* until we enable them back, at which point we will have disabled the timeout
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* so the completion routine will not be called twice. */
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if(i2c_head->tmo_ms > 0)
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timeout_cancel(&i2c_tmo);
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/* notify completion and unqueue
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* WARNING completion callback can queue other transfers, so the only part
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* of the queue that cannot change is this transaction, everything else can
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* change */
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struct imx233_i2c_xfer_t *this_xfer = i2c_head;
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struct imx233_i2c_xfer_t *last_xfer = i2c_head->last; /* in transaction */
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/* unqueue head */
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imx233_i2c_unqueue_head(status);
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/* in case of failure, skip others */
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if(status != I2C_SUCCESS && this_xfer != last_xfer)
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while(i2c_head != last_xfer)
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imx233_i2c_unqueue_head(I2C_SKIP);
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/* if there is anything left, start it */
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if(i2c_head)
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imx233_i2c_start();
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}
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static int imx233_i2c_timeout(struct timeout *tmo)
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{
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(void) tmo;
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imx233_i2c_abort();
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return 0; /* do not fire again */
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}
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void imx233_i2c_transfer(struct imx233_i2c_xfer_t *xfer)
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{
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/* avoid any race with the irq handler */
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unsigned long cpsr = disable_irq_save();
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/* before queuing, update link to last transfer in each transfer */
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struct imx233_i2c_xfer_t *last = xfer;
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while(last->next)
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last = last->next;
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struct imx233_i2c_xfer_t *tmp = xfer;
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while(tmp)
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{
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tmp->last = last;
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tmp = tmp->next;
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}
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/* no transfer pending: start one */
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if(i2c_head == NULL)
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{
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i2c_head = xfer;
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i2c_tail = last;
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/* kick transfer now */
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imx233_i2c_start();
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}
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/* pending transer: queue and let the irq handler process it for us */
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else
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{
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i2c_tail->next = xfer;
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i2c_tail = last;
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}
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restore_irq(cpsr);
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}
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/**
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* DMA API implementation
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*/
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/* Used for DMA */
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@ -53,7 +213,7 @@ struct i2c_dma_command_t
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struct apb_dma_command_t dma;
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/* PIO words */
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uint32_t ctrl0;
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/* copy buffer copy */
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/* copy buffer pointers */
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void *src;
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void *dst;
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/* padded to next multiple of cache line size (32 bytes) */
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@ -67,31 +227,9 @@ __ENSURE_STRUCT_CACHE_FRIENDLY(struct i2c_dma_command_t)
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/* Current transfer */
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static int i2c_nr_stages;
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static struct i2c_dma_command_t i2c_stage[I2C_NR_STAGES];
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static struct mutex i2c_mutex;
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static struct semaphore i2c_sema;
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static uint8_t i2c_buffer[I2C_BUFFER_SIZE] CACHEALIGN_ATTR;
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static uint32_t i2c_buffer_end; /* current end */
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void INT_I2C_DMA(void)
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{
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_I2C))
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imx233_dma_reset_channel(APB_I2C);
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_I2C);
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semaphore_release(&i2c_sema);
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}
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void INT_I2C_ERROR(void)
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{
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_I2C))
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imx233_dma_reset_channel(APB_I2C);
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_I2C);
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semaphore_release(&i2c_sema);
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}
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static void imx233_i2c_reset(void)
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{
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/* clear softreset */
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@ -107,10 +245,6 @@ static void imx233_i2c_reset(void)
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BF_SET(I2C_CTRL1, ACK_MODE);
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#endif
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BF_SET(I2C_CTRL0, CLKGATE);
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/* Fast-mode @ 400K */
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HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */
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HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */
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HW_I2C_TIMING2 = 0x0015000D;
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}
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void imx233_i2c_init(void)
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@ -120,31 +254,27 @@ void imx233_i2c_init(void)
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imx233_pinctrl_setup_vpin(VPIN_I2C_SCL, "i2c scl", PINCTRL_DRIVE_4mA, true);
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imx233_pinctrl_setup_vpin(VPIN_I2C_SDA, "i2c sda", PINCTRL_DRIVE_4mA, true);
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imx233_i2c_reset();
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mutex_init(&i2c_mutex);
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semaphore_init(&i2c_sema, 1, 0);
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i2c_head = i2c_tail = NULL;
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}
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void imx233_i2c_begin(void)
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static void imx233_i2c_begin(void)
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{
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mutex_lock(&i2c_mutex);
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/* wakeup */
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BF_CLR(I2C_CTRL0, CLKGATE);
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i2c_nr_stages = 0;
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i2c_buffer_end = 0;
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}
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enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop)
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static void imx233_i2c_add(bool start, bool transmit,
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void *buffer, unsigned size, bool stop)
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{
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if(i2c_nr_stages == I2C_NR_STAGES)
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return I2C_ERROR;
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panicf("i2c: too many stages");
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/* align buffer end on cache boundary */
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uint32_t start_off = CACHEALIGN_UP(i2c_buffer_end);
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uint32_t end_off = start_off + size;
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if(end_off > I2C_BUFFER_SIZE)
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{
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panicf("die");
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return I2C_BUFFER_FULL;
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}
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panicf("i2c: transfer is too big");
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i2c_buffer_end = end_off;
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if(transmit)
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{
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@ -175,7 +305,6 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer,
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XFER_COUNT(size), DIRECTION(transmit), SEND_NAK_ON_LAST(!transmit),
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PRE_SEND_START(start), POST_SEND_STOP(stop), MASTER_MODE(1));
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i2c_nr_stages++;
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return I2C_SUCCESS;
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}
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static enum imx233_i2c_error_t imx233_i2c_finalize(void)
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@ -190,10 +319,10 @@ static enum imx233_i2c_error_t imx233_i2c_finalize(void)
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return I2C_SUCCESS;
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}
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enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
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static void imx233_i2c_kick(void)
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{
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if(i2c_nr_stages == 0)
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return I2C_ERROR;
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panicf("i2c: empty kick");
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i2c_stage[i2c_nr_stages - 1].dma.cmd |= BM_APB_CHx_CMD_SEMAPHORE | BM_APB_CHx_CMD_IRQONCMPLT;
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BF_CLR(I2C_CTRL1, SLAVE_IRQ, SLAVE_STOP_IRQ, MASTER_LOSS_IRQ, EARLY_TERM_IRQ,
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@ -203,15 +332,24 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
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imx233_icoll_enable_interrupt(INT_SRC_I2C_ERROR, true);
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imx233_dma_enable_channel_interrupt(APB_I2C, true);
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imx233_dma_start_command(APB_I2C, &i2c_stage[0].dma);
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}
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enum imx233_i2c_error_t ret;
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if(semaphore_wait(&i2c_sema, timeout) == OBJ_WAIT_TIMEDOUT)
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{
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static void imx233_i2c_abort(void)
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{
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/* FIXME there is a race condition here: if dma irq fires right before we
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* reset the channel, it will most likely trigger an IRQ anyway. It is
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* extremely unlikely but ideally, we should check this in the IRQ handler
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* with an id/counter. */
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imx233_dma_reset_channel(APB_I2C);
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imx233_i2c_reset();
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ret = I2C_TIMEOUT;
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}
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else if(BF_RD(I2C_CTRL1, MASTER_LOSS_IRQ))
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imx233_i2c_transfer_complete(I2C_TIMEOUT);
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}
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static enum imx233_i2c_error_t imx233_i2c_end(void)
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{
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enum imx233_i2c_error_t ret;
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/* check for various errors */
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if(BF_RD(I2C_CTRL1, MASTER_LOSS_IRQ))
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ret = I2C_MASTER_LOSS;
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else if(BF_RD(I2C_CTRL1, NO_SLAVE_ACK_IRQ))
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{
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@ -229,48 +367,132 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
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ret = imx233_i2c_finalize();
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/* sleep */
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BF_SET(I2C_CTRL0, CLKGATE);
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mutex_unlock(&i2c_mutex);
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return ret;
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}
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static void imx233_i2c_set_speed(bool fast_mode)
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{
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/* See I2C specification for standard- and fast-mode timings
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* Clock is derived APBX which we assume to be running at 24 MHz. */
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if(fast_mode)
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{
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/* Fast-mode @ 400 kHz */
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HW_I2C_TIMING0 = 0x000f0007; /* HIGH_COUNT=0.6us, RCV_COUNT=0.2us */
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HW_I2C_TIMING1 = 0x001f000f; /* LOW_COUNT=1.3us, XMIT_COUNT=0.6us */
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HW_I2C_TIMING2 = 0x0015000d; /* BUS_FREE=0.9us LEADIN_COUNT=0.55us */
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}
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else
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{
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/* Standard-mode @ 100 kHz */
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HW_I2C_TIMING0 = 0x00780030; /* HIGH_COUNT=5us, RCV_COUNT=2us */
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HW_I2C_TIMING1 = 0x00800030; /* LOW_COUNT=5.3us, XMIT_COUNT=2us */
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HW_I2C_TIMING2 = 0x00300030; /* BUS_FREE=2us LEADIN_COUNT=2us */
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}
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}
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static void imx233_i2c_irq(bool err)
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{
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if(err)
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panicf("i2c: dma error");
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_I2C))
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imx233_dma_reset_channel(APB_I2C);
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_I2C);
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/* handle completion */
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imx233_i2c_transfer_complete(imx233_i2c_end());
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}
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void INT_I2C_DMA(void)
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{
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imx233_i2c_irq(false);
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}
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void INT_I2C_ERROR(void)
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{
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imx233_i2c_irq(true);
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}
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/** Public API */
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void i2c_init(void)
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{
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}
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struct imx233_i2c_sync_xfer_t
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{
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struct imx233_i2c_xfer_t xfer;
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struct semaphore sema;
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volatile enum imx233_i2c_error_t status;
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};
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/* synchronous callback: record status and release semaphore */
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static void i2c_sync_callback(struct imx233_i2c_xfer_t *xfer, enum imx233_i2c_error_t status)
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{
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struct imx233_i2c_sync_xfer_t *sxfer = (void *)xfer;
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sxfer->status = status;
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semaphore_release(&sxfer->sema);
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}
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static int i2c_sync_transfer(struct imx233_i2c_sync_xfer_t *xfer)
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{
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semaphore_init(&xfer->sema, 1, 0);
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/* common init */
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xfer->xfer.next = NULL;
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xfer->xfer.callback = &i2c_sync_callback;
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xfer->xfer.fast_mode = true;
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xfer->xfer.tmo_ms = 1000;
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/* kick */
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imx233_i2c_transfer(&xfer->xfer);
|
||||
/* wait */
|
||||
semaphore_wait(&xfer->sema, TIMEOUT_BLOCK);
|
||||
return (int)xfer->status;
|
||||
}
|
||||
|
||||
int i2c_write(int device, const unsigned char* buf, int count)
|
||||
{
|
||||
uint8_t addr = device;
|
||||
imx233_i2c_begin();
|
||||
imx233_i2c_add(true, true, &addr, 1, false); /* start + dev addr */
|
||||
imx233_i2c_add(false, true, (void *)buf, count, true); /* data + stop */
|
||||
return imx233_i2c_end(10);
|
||||
struct imx233_i2c_sync_xfer_t xfer;
|
||||
xfer.xfer.dev_addr = device;
|
||||
xfer.xfer.mode = I2C_WRITE;
|
||||
xfer.xfer.count[0] = count;
|
||||
xfer.xfer.data[0] = (void *)buf;
|
||||
xfer.xfer.count[1] = 0;
|
||||
return i2c_sync_transfer(&xfer);
|
||||
}
|
||||
|
||||
int i2c_read(int device, unsigned char* buf, int count)
|
||||
{
|
||||
uint8_t addr = device | 1;
|
||||
imx233_i2c_begin();
|
||||
imx233_i2c_add(true, true, &addr, 1, false); /* start + dev addr */
|
||||
imx233_i2c_add(false, false, buf, count, true); /* data + stop */
|
||||
return imx233_i2c_end(10);
|
||||
struct imx233_i2c_sync_xfer_t xfer;
|
||||
xfer.xfer.dev_addr = device;
|
||||
xfer.xfer.mode = I2C_READ;
|
||||
xfer.xfer.count[0] = 0;
|
||||
xfer.xfer.count[1] = count;
|
||||
xfer.xfer.data[1] = buf;
|
||||
return i2c_sync_transfer(&xfer);
|
||||
}
|
||||
|
||||
int i2c_readmem(int device, int address, unsigned char* buf, int count)
|
||||
{
|
||||
uint8_t start[2] = {device, address};
|
||||
uint8_t addr_rd = device | 1;
|
||||
imx233_i2c_begin();
|
||||
imx233_i2c_add(true, true, start, 2, false); /* start + dev addr + addr */
|
||||
imx233_i2c_add(true, true, &addr_rd, 1, false); /* start + dev addr */
|
||||
imx233_i2c_add(false, false, buf, count, true); /* data + stop */
|
||||
return imx233_i2c_end(10);
|
||||
uint8_t addr = address; /* assume 1 byte */
|
||||
struct imx233_i2c_sync_xfer_t xfer;
|
||||
xfer.xfer.dev_addr = device;
|
||||
xfer.xfer.mode = I2C_READ;
|
||||
xfer.xfer.count[0] = 1;
|
||||
xfer.xfer.data[0] = &addr;
|
||||
xfer.xfer.count[1] = count;
|
||||
xfer.xfer.data[1] = buf;
|
||||
return i2c_sync_transfer(&xfer);
|
||||
}
|
||||
|
||||
int i2c_writemem(int device, int address, const unsigned char* buf, int count)
|
||||
{
|
||||
uint8_t start[2] = {device, address};
|
||||
imx233_i2c_begin();
|
||||
imx233_i2c_add(true, true, start, 2, false); /* start + dev addr + addr */
|
||||
imx233_i2c_add(false, true, (void *)buf, count, true); /* data + stop */
|
||||
return imx233_i2c_end(10);
|
||||
uint8_t addr = address; /* assume 1 byte */
|
||||
struct imx233_i2c_sync_xfer_t xfer;
|
||||
xfer.xfer.dev_addr = device;
|
||||
xfer.xfer.mode = I2C_WRITE;
|
||||
xfer.xfer.count[0] = 1;
|
||||
xfer.xfer.data[0] = &addr;
|
||||
xfer.xfer.count[1] = count;
|
||||
xfer.xfer.data[1] = (void *)buf;
|
||||
return i2c_sync_transfer(&xfer);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
#include "cpu.h"
|
||||
#include "system.h"
|
||||
#include "system-target.h"
|
||||
#include "i2c.h"
|
||||
|
||||
enum imx233_i2c_error_t
|
||||
{
|
||||
|
|
@ -35,14 +34,71 @@ enum imx233_i2c_error_t
|
|||
I2C_NO_SLAVE_ACK = -4,
|
||||
I2C_SLAVE_NAK = -5,
|
||||
I2C_BUFFER_FULL = -6,
|
||||
I2C_SKIP = -7, /* transfer skipped before of previous error in transaction */
|
||||
};
|
||||
|
||||
/** Important notes on the driver.
|
||||
*
|
||||
* The driver supports both synchronous and asynchronous transfers. Asynchronous
|
||||
* transfer functions can safely be called from IRQ context. Beware that the completion
|
||||
* callback of asynchronous transfers may be called from IRQ context.
|
||||
*
|
||||
* The driver supports queuing so it is safe to call several transfer functions
|
||||
* concurrently.
|
||||
*/
|
||||
|
||||
void imx233_i2c_init(void);
|
||||
/* start building a transfer, will acquire an exclusive lock */
|
||||
void imx233_i2c_begin(void);
|
||||
/* add stage */
|
||||
enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop);
|
||||
/* end building a transfer and start the transfer */
|
||||
enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout);
|
||||
|
||||
/** legacy API:
|
||||
* read/write functions return 0 on success */
|
||||
int i2c_write(int device, const unsigned char* buf, int count);
|
||||
int i2c_read(int device, unsigned char* buf, int count);
|
||||
int i2c_readmem(int device, int address, unsigned char* buf, int count);
|
||||
int i2c_writemem(int device, int address, const unsigned char* buf, int count);
|
||||
|
||||
/** Advanced API */
|
||||
struct imx233_i2c_xfer_t;
|
||||
typedef void (*imx233_i2c_cb_t)(struct imx233_i2c_xfer_t *xfer, enum imx233_i2c_error_t status);
|
||||
|
||||
/** Transfer mode. There are currently two types of transfers, to make
|
||||
* programming simpler:
|
||||
* - write: write count[0] bytes from data[0], and then count[1] bytes from data[1]
|
||||
* (if count[1] > 0). The second stage is useful to avoid allocating a single
|
||||
* buffer to hold address + data for example.
|
||||
* - read: write count[0] bytes from data[0], and then read count[1] bytes from data[1].
|
||||
* If count[0] = 0 then the write stage is ignored.
|
||||
*/
|
||||
enum imx233_i2x_xfer_mode_t
|
||||
{
|
||||
I2C_WRITE,
|
||||
I2C_READ,
|
||||
};
|
||||
|
||||
/** This data structure represents one transfer. The exact shape of the transfer
|
||||
* depends on the mode.
|
||||
* NOTE a single transfer is limited to 512 bytes of data (RX + TX)
|
||||
* A transaction is made up of several transfers, chained together.
|
||||
*/
|
||||
struct imx233_i2c_xfer_t
|
||||
{
|
||||
struct imx233_i2c_xfer_t *next; /* next transfer, or NULL */
|
||||
imx233_i2c_cb_t callback; /* NULL for no callack */
|
||||
int dev_addr; /* device address */
|
||||
bool fast_mode; /* 400 kHz 'fast' mode or 100 kHz 'normal' mode */
|
||||
enum imx233_i2x_xfer_mode_t mode; /* transfer mode */
|
||||
int count[2]; /* count: depends on mode */
|
||||
void *data[2]; /* data: depends on mode */
|
||||
unsigned tmo_ms; /* timeout in milliseconds (0 means infinite) */
|
||||
/* internal */
|
||||
struct imx233_i2c_xfer_t *last; /* last in transaction */
|
||||
};
|
||||
|
||||
/* Queue one or more tranfer. If several transfer are queued (transaction)
|
||||
* they are guaranteed to be executed "as one" (ie without interleaving). Furthermore,
|
||||
* if a transfer of the transfaction fails, the remaining transfers of the transactions
|
||||
* will NOT be executed (and their callback will be called with SKIP status).
|
||||
* Return 0 if queueing was successful. Note that the transfer may still fail,
|
||||
* in which case the callback will have a nonzero status code. */
|
||||
void imx233_i2c_transfer(struct imx233_i2c_xfer_t *xfer);
|
||||
|
||||
#endif // __I2C_IMX233_H__
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue