devs/foxbox
1
0
Fork 0
forked from len0rd/rockbox
Code Pull requests Activity

Shorten the uncontended (expected) corelock_(try_)lock return path. Squeeze down corelock_try_lock by a couple instructions.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16983 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-04-06 08:48:31 +00:00
parent 22c8a25f5f
commit 4ab52c3456
1 changed files with 17 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

34
firmware/thread.c
View file

@ -276,17 +276,19 @@ void corelock_init(struct corelock *cl)
void corelock_lock(struct corelock *cl) __attribute__((naked)); void corelock_lock(struct corelock *cl) __attribute__((naked));
void corelock_lock(struct corelock *cl) void corelock_lock(struct corelock *cl)
{ {
/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
asm volatile ( asm volatile (
"mov r1, %0 \n" /* r1 = PROCESSOR_ID */ "mov r1, %0 \n" /* r1 = PROCESSOR_ID */
"ldrb r1, [r1] \n" "ldrb r1, [r1] \n"
"strb r1, [r0, r1, lsr #7] \n" /* cl->myl[core] = core */ "strb r1, [r0, r1, lsr #7] \n" /* cl->myl[core] = core */
"and r2, r1, #1 \n" /* r2 = othercore */ "eor r2, r1, #0xff \n" /* r2 = othercore */
"strb r2, [r0, #2] \n" /* cl->turn = othercore */ "strb r2, [r0, #2] \n" /* cl->turn = othercore */
"1: \n" "1: \n"
"ldrb r3, [r0, r2] \n" /* cl->myl[othercore] == 0 ? */ "ldrb r3, [r0, r2, lsr #7] \n" /* cl->myl[othercore] == 0 ? */
"cmp r3, #0 \n" "cmp r3, #0 \n" /* yes? lock acquired */
"ldrneb r3, [r0, #2] \n" /* || cl->turn == core ? */ "bxeq lr \n"
"cmpne r3, r1, lsr #7 \n" "ldrb r3, [r0, #2] \n" /* || cl->turn == core ? */
"cmp r3, r1 \n"
"bxeq lr \n" /* yes? lock acquired */ "bxeq lr \n" /* yes? lock acquired */
"b 1b \n" /* keep trying */ "b 1b \n" /* keep trying */
: : "i"(&PROCESSOR_ID) : : "i"(&PROCESSOR_ID)
@ -301,23 +303,21 @@ void corelock_lock(struct corelock *cl)
int corelock_try_lock(struct corelock *cl) __attribute__((naked)); int corelock_try_lock(struct corelock *cl) __attribute__((naked));
int corelock_try_lock(struct corelock *cl) int corelock_try_lock(struct corelock *cl)
{ {
/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
asm volatile ( asm volatile (
"mov r1, %0 \n" /* r1 = PROCESSOR_ID */ "mov r1, %0 \n" /* r1 = PROCESSOR_ID */
"ldrb r1, [r1] \n" "ldrb r1, [r1] \n"
"mov r3, r0 \n"
"strb r1, [r0, r1, lsr #7] \n" /* cl->myl[core] = core */ "strb r1, [r0, r1, lsr #7] \n" /* cl->myl[core] = core */
"and r2, r1, #1 \n" /* r2 = othercore */ "eor r2, r1, #0xff \n" /* r2 = othercore */
"strb r2, [r0, #2] \n" /* cl->turn = othercore */ "strb r2, [r0, #2] \n" /* cl->turn = othercore */
"1: \n" "ldrb r0, [r3, r2, lsr #7] \n" /* cl->myl[othercore] == 0 ? */
"ldrb r3, [r0, r2] \n" /* cl->myl[othercore] == 0 ? */ "eors r0, r0, r2 \n" /* yes? lock acquired */
"cmp r3, #0 \n" "bxne lr \n"
"ldrneb r3, [r0, #2] \n" /* || cl->turn == core? */ "ldrb r0, [r3, #2] \n" /* || cl->turn == core? */
"cmpne r3, r1, lsr #7 \n" "ands r0, r0, r1 \n"
"moveq r0, #1 \n" /* yes? lock acquired */ "streqb r0, [r3, r1, lsr #7] \n" /* if not, cl->myl[core] = 0 */
"bxeq lr \n" "bx lr \n" /* return result */
"mov r2, #0 \n" /* cl->myl[core] = 0 */
"strb r2, [r0, r1, lsr #7] \n"
"mov r0, r2 \n"
"bx lr \n" /* acquisition failed */
: : "i"(&PROCESSOR_ID) : : "i"(&PROCESSOR_ID)
); );