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Hopefully fix FS #8840 for iAudio M3, M5 and X5. Reduce greyscale update frequency on M3 in order to reduce CPU load (was >50% before, but this fix would have made it even worse).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17621 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2008-05-24 08:53:12 +00:00
parent 5e9732367d
commit 4a6190dd13
3 changed files with 134 additions and 85 deletions
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8
apps/plugins/lib/grey_core.c
View file

@ -81,10 +81,10 @@ static const unsigned char lcdlinear[256] = {
220, 221, 222, 223, 225, 226, 227, 228, 229, 230, 231, 232, 234, 235, 236, 237, 220, 221, 222, 223, 225, 226, 227, 228, 229, 230, 231, 232, 234, 235, 236, 237,
238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 249, 250, 251, 252 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 249, 250, 251, 252
}; };
/* The actual LCD scanrate is twice as high, but we cannot transfer fast enough /* The actual LCD scanrate is 3x as high, but 150 Hz or 75 Hz cause a too high
* for 150Hz. Even at 75Hz, greyscale display is very smooth. Average from * CPU load (> 50 %). Even at 50Hz, greyscale display is rather smooth. Average
* 2 iAudio remotes. */ * from 2 iAudio remotes. */
#define LCD_SCANRATE 75 /* Hz */ #define LCD_SCANRATE 50 /* Hz */
#elif defined IAUDIO_M5 /* verified */ #elif defined IAUDIO_M5 /* verified */
/* Measurement of one iAudio M5L */ /* Measurement of one iAudio M5L */

84
firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S
View file

@ -58,15 +58,15 @@
swap %d3 /* Shift data to upper byte */ swap %d3 /* Shift data to upper byte */
lsl.l #8, %d3 lsl.l #8, %d3
eor.l %d7, %d0 /* precalculate opposite state of clock line */ move.l %d0, %d1 /* precalculate opposite state of clock line */
eor.l %d7, %d1
lsl.l #1, %d3 /* Shift out MSB */ lsl.l #1, %d3 /* Shift out MSB */
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */ eor.l %d6, %d0 /* 1: Flip data bit */
eor.l %d6, %d1
1: 1:
move.l %d0, (%a0) /* Output new state and set CLK = 0*/ move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
bra.w .wr_bit7 bra.w .wr_bit7
@ -98,62 +98,77 @@
eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ eor.l %d1, %d3 /* previous state, and 0's where it doesn't */
swap %d3 /* Shift data to upper word */ swap %d3 /* Shift data to upper word */
eor.l %d7, %d0 /* precalculate opposite state of clock line */ move.l %d0, %d1 /* precalculate opposite state of clock line */
eor.l %d7, %d1
lsl.l #1, %d3 /* Shift out MSB */ lsl.l #1, %d3 /* Shift out MSB */
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */ eor.l %d6, %d0 /* 1: Flip data bit */
eor.l %d6, %d1
1: 1:
move.l %d0, (%a0) /* Output new state and set CLK = 0*/ move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
nop
.macro bit_out .macro bit_out
move.l %d0, (%a0) /* Set CLK = 1 */
lsl.l #1, %d3 lsl.l #1, %d3
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 eor.l %d6, %d0
eor.l %d6, %d1
1: 1:
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ move.l %d1, (%a0)
move.l %d0, (%a0)
move.l %d0, %d1
eor.l %d7, %d1
.endm .endm
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
.wr_bit7: .wr_bit7:
bit_out
nop nop
bit_out bit_out
nop nop
bit_out
nop nop
bit_out bit_out
nop nop
bit_out
nop nop
bit_out bit_out
nop nop
nop
bit_out bit_out
nop nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
nop move.l %d0, (%a0) /* Set CLK = 1 */
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
move.w %d2, %sr move.w %d2, %sr
rts rts
@ -195,6 +210,7 @@
move.l %d1, (%a0) /* Output new state and set CLK = 0*/ move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, (%a0) /* set CLK = 1 */ move.l %d0, (%a0) /* set CLK = 1 */
.endm .endm
bit_out_fast bit_out_fast
bit_out_fast bit_out_fast
bit_out_fast bit_out_fast

113
firmware/target/coldfire/iaudio/m3/lcd-as-m3.S
View file

@ -58,15 +58,15 @@
swap %d3 /* Shift data to upper byte */ swap %d3 /* Shift data to upper byte */
lsl.l #8, %d3 lsl.l #8, %d3
eor.l %d7, %d0 /* precalculate opposite state of clock line */ move.l %d0, %d1 /* precalculate opposite state of clock line */
eor.l %d7, %d1
lsl.l #1, %d3 /* Shift out MSB */ lsl.l #1, %d3 /* Shift out MSB */
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */ eor.l %d6, %d0 /* 1: Flip data bit */
eor.l %d6, %d1
1: 1:
move.l %d0, (%a0) /* Output new state and set CLK = 0*/ move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
bra.w .wr_bit7 bra.w .wr_bit7
@ -98,62 +98,77 @@
eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ eor.l %d1, %d3 /* previous state, and 0's where it doesn't */
swap %d3 /* Shift data to upper word */ swap %d3 /* Shift data to upper word */
eor.l %d7, %d0 /* precalculate opposite state of clock line */ move.l %d0, %d1 /* precalculate opposite state of clock line */
eor.l %d7, %d1
lsl.l #1, %d3 /* Shift out MSB */ lsl.l #1, %d3 /* Shift out MSB */
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */ eor.l %d6, %d0 /* 1: Flip data bit */
eor.l %d6, %d1
1: 1:
move.l %d0, (%a0) /* Output new state and set CLK = 0*/ move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
nop
.macro bit_out .macro bit_out
move.l %d0, (%a0) /* Set CLK = 1 */
lsl.l #1, %d3 lsl.l #1, %d3
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 eor.l %d6, %d0
eor.l %d6, %d1
1: 1:
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ move.l %d1, (%a0)
move.l %d0, (%a0)
move.l %d0, %d1
eor.l %d7, %d1
.endm .endm
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
bit_out
nop
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
.wr_bit7: .wr_bit7:
bit_out
nop nop
bit_out bit_out
nop nop
bit_out
nop nop
bit_out bit_out
nop nop
bit_out
nop nop
bit_out bit_out
nop nop
nop
bit_out bit_out
nop nop
nop
bit_out
nop
nop
bit_out
nop
nop
bit_out
nop
nop
nop move.l %d0, (%a0) /* Set CLK = 1 */
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
move.w %d2, %sr move.w %d2, %sr
rts rts
@ -195,6 +210,7 @@
move.l %d1, (%a0) /* Output new state and set CLK = 0*/ move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, (%a0) /* set CLK = 1 */ move.l %d0, (%a0) /* set CLK = 1 */
.endm .endm
bit_out_fast bit_out_fast
bit_out_fast bit_out_fast
bit_out_fast bit_out_fast
@ -438,33 +454,41 @@ lcd_grey_data:
eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ eor.l %d1, %d3 /* previous state, and 0's where it doesn't */
swap %d3 /* Shift data to upper word */ swap %d3 /* Shift data to upper word */
eor.l %d7, %d0 /* precalculate opposite state of clock line */ move.l %d0, %d1 /* precalculate opposite state of clock line */
eor.l %d7, %d1
lsl.l #1, %d3 /* Shift out MSB */ lsl.l #1, %d3 /* Shift out MSB */
bcc.s 1f bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */ eor.l %d6, %d0 /* 1: Flip data bit */
eor.l %d6, %d1
1: 1:
move.l %d0, %d1 move.l %d1, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
eor.l %d7, %d1
move.l (%a3), %d4 /* fetch 4 pixel phases */ move.l (%a3), %d4 /* fetch 4 pixel phases */
bit_out bit_out
bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */
seq.b %d5 /* %d5 = ........................00000000 */ seq.b %d5 /* %d5 = ........................00000000 */
lsl.l #1, %d5 /* %d5 = .......................00000000. */ lsl.l #1, %d5 /* %d5 = .......................00000000. */
trapf
trapf
bit_out bit_out
bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */
seq.b %d5 /* %d5 = .......................011111111 */ seq.b %d5 /* %d5 = .......................011111111 */
lsl.l #1, %d5 /* %d5 = ......................011111111. */ lsl.l #1, %d5 /* %d5 = ......................011111111. */
trapf
trapf
bit_out bit_out
bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */ bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */
seq.b %d5 /* %d5 = ......................0122222222 */ seq.b %d5 /* %d5 = ......................0122222222 */
lsl.l #1, %d5 /* %d5 = .....................0122222222. */ lsl.l #1, %d5 /* %d5 = .....................0122222222. */
trapf
trapf
bit_out bit_out
bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */ bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */
seq.b %d5 /* %d5 = .....................01233333333 */ seq.b %d5 /* %d5 = .....................01233333333 */
lsl.l #1, %d5 /* %d5 = ....................01233333333. */ lsl.l #1, %d5 /* %d5 = ....................01233333333. */
trapf
trapf
bit_out bit_out
add.l (%a2)+, %d4 /* add 4 pixel values to the phases */ add.l (%a2)+, %d4 /* add 4 pixel values to the phases */
bit_out bit_out
@ -476,18 +500,26 @@ lcd_grey_data:
bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */
seq.b %d5 /* %d5 = ....................012344444444 */ seq.b %d5 /* %d5 = ....................012344444444 */
lsl.l #1, %d5 /* %d5 = ...................012344444444. */ lsl.l #1, %d5 /* %d5 = ...................012344444444. */
trapf
trapf
bit_out bit_out
bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */
seq.b %d5 /* %d5 = ...................0123455555555 */ seq.b %d5 /* %d5 = ...................0123455555555 */
lsl.l #1, %d5 /* %d5 = ..................0123455555555. */ lsl.l #1, %d5 /* %d5 = ..................0123455555555. */
trapf
trapf
bit_out bit_out
bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */ bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */
seq.b %d5 /* %d5 = ..................01234566666666 */ seq.b %d5 /* %d5 = ..................01234566666666 */
lsl.l #1, %d5 /* %d5 = .................01234566666666. */ lsl.l #1, %d5 /* %d5 = .................01234566666666. */
trapf
trapf
bit_out bit_out
bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */ bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */
seq.b %d5 /* %d5 = .................012345677777777 */ seq.b %d5 /* %d5 = .................012345677777777 */
lsr.l #7, %d5 /* %d5 = ........................01234567 */ lsr.l #7, %d5 /* %d5 = ........................01234567 */
trapf
trapf
bit_out bit_out
add.l (%a2)+, %d4 /* add 4 pixel values to the phases */ add.l (%a2)+, %d4 /* add 4 pixel values to the phases */
bit_out bit_out
@ -495,13 +527,14 @@ lcd_grey_data:
bit_out bit_out
nop nop
nop
bit_out bit_out
move.l %d5, %d3 move.l %d5, %d3
lsl.l #8, %d3 lsl.l #8, %d3
or.l %d5, %d3 or.l %d5, %d3
nop nop
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
move.l %d0, (%a0) /* Set CLK = 1 */
move.w %d2, %sr move.w %d2, %sr
cmp.l %a3, %a4 cmp.l %a3, %a4