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Update as3525 i2c register description

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21018 a1c6a512-1295-4272-9138-f99709370657
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Bertrik Sikken 2009-05-21 18:31:50 +00:00
parent 442726339a
commit 4a4639e157
1 changed files with 8 additions and 1 deletions
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firmware/target/arm/as3525/ascodec-as3525.c
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@ -27,7 +27,14 @@
I2C register description: I2C register description:
* I2C2_CNTRL needs to be set to 0x51 for transfers to work at all. * I2C2_CNTRL needs to be set to 0x51 for transfers to work at all.
bit 1 indicates direction of transfer (0 = write, 1 = read) bit 0: ? possibly related to using ACKs during transfers
bit 1: direction of transfer (0 = write, 1 = read)
bit 2: use 2-byte slave address
* I2C2_IMR, I2C2_RIS, I2C2_MIS, I2C2_INT_CLR interrupt bits:
bit 2: byte read interrupt
bit 3: byte write interrupt
bit 4: ? possibly some kind of error status
bit 7: ACK error
* I2C2_SR (status register) indicates in bit 0 if a transfer is busy. * I2C2_SR (status register) indicates in bit 0 if a transfer is busy.
* I2C2_SLAD0 contains the i2c slave address to read from / write to. * I2C2_SLAD0 contains the i2c slave address to read from / write to.
* I2C2_CPSR0/1 is the divider from the peripheral clock to the i2c clock. * I2C2_CPSR0/1 is the divider from the peripheral clock to the i2c clock.