forked from len0rd/rockbox
as3525v2: full list of registers + description
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24825 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
34ae3959e6
commit
48ed5ad66e
1 changed files with 77 additions and 80 deletions
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@ -68,36 +68,6 @@ static void printf(const char *format, ...)
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/* controller registers */
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#define SD_BASE 0xC6070000
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/*
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* REGISTERS
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*
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* m = modify (orr/bic), r = read, w = write
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*
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* 00 m/r/w
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* 04 m/w
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* 08 m
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* 0C ?
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* 10 r/w
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* 14 w
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* 18 m
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* 1C w ==> set a bit before transfer (sometimes) !
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* 20 w ==> set a bit before transfer !
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* 24 w irq mask ?
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* 28 w arg
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* 2C r/w cmd
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* 30 r resp0
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* 34 r resp1
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* 38 r resp2
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* 3C r resp3
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* 40 r irq status (only read in isr)
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* 44 m/w irq clear
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* 48 r
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* 4C m
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* 64 w
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* 70 r
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* 100 FIFO
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*/
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/*
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* STATUS register
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* & 0xBA80
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@ -165,23 +135,50 @@ static void printf(const char *format, ...)
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*
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*/
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/* FIXME */
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#define MCI_POWER
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#define MCI_CLOCK
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#define MCI_ARGUMENT (*(volatile unsigned long *) (SD_BASE+0x28))
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#define MCI_COMMAND (*(volatile unsigned long *) (SD_BASE+0x2C))
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#define MCI_RESPCMD
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#define MCI_RESP0 (*(volatile unsigned long *) (SD_BASE+0x30))
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#define MCI_RESP1 (*(volatile unsigned long *) (SD_BASE+0x34))
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#define MCI_RESP2 (*(volatile unsigned long *) (SD_BASE+0x38))
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#define MCI_RESP3 (*(volatile unsigned long *) (SD_BASE+0x3C))
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#define MCI_DATA_TIMER
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#define MCI_DATA_LENGTH
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#define MCI_DATA_CTRL
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#define MCI_STATUS (*(volatile unsigned long *) (SD_BASE+0x40))
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#define MCI_CLEAR (*(volatile unsigned long *) (SD_BASE+0x44))
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#define MCI_MASK (*(volatile unsigned long *) (SD_BASE+0x24))
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#define MCI_SELECT
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#define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
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#define MCI_CTRL SD_REG(0x00)
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#define MCI_PWREN SD_REG(0x04) /* power enable */
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#define MCI_CLKDIV SD_REG(0x08) /* clock divider */
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#define MCI_CLKSRC SD_REG(0x0C) /* clock source */
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#define MCI_CLKENA SD_REG(0x10) /* clock enable */
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#define MCI_TMOUT SD_REG(0x14) /* timeout */
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#define MCI_CTYPE SD_REG(0x18) /* card type */
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#define MCI_BLKSIZ SD_REG(0x1C) /* block size */
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#define MCI_BYTCNT SD_REG(0x20) /* byte count */
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#define MCI_MASK SD_REG(0x24) /* interrupt mask */
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#define MCI_ARGUMENT SD_REG(0x28)
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#define MCI_COMMAND SD_REG(0x2C)
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#define MCI_RESP0 SD_REG(0x30)
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#define MCI_RESP1 SD_REG(0x34)
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#define MCI_RESP2 SD_REG(0x38)
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#define MCI_RESP3 SD_REG(0x3C)
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#define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */
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#define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
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* status clear */
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#define MCI_STATUS SD_REG(0x48)
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#define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */
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#define MCI_CDETECT SD_REG(0x50) /* card detect */
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#define MCI_WRTPRT SD_REG(0x54) /* write protect */
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#define MCI_GPIO SD_REG(0x58)
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#define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count */
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#define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes */
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#define MCI_DEBNCE SD_REG(0x64) /* card detect debounce */
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#define MCI_USRID SD_REG(0x68) /* user id */
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#define MCI_VERID SD_REG(0x6C) /* version id */
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#define MCI_HCON SD_REG(0x70) /* hardware config */
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#define MCI_BMOD SD_REG(0x80) /* bus mode */
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#define MCI_PLDMND SD_REG(0x84) /* poll demand */
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#define MCI_DBADDR SD_REG(0x88) /* descriptor base address */
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#define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */
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#define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */
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#define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */
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#define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */
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#define MCI_ERROR 0 /* FIXME */
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@ -220,7 +217,7 @@ static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
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void INT_NAND(void)
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{
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(*(volatile unsigned long *) (SD_BASE+0x0)) &= ~0x10; // ?
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MCI_CTRL &= ~0x10; // ?
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const int status = MCI_STATUS;
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#if 0
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@ -229,7 +226,7 @@ void INT_NAND(void)
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#endif
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// wakeup_signal(&transfer_completion_signal);
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MCI_CLEAR = status;
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MCI_RAW_STATUS = status;
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//static int x = 0;
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switch(status)
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@ -264,11 +261,11 @@ void INT_NAND(void)
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* read resp (6, 7, 12, 42) : while bit 9 is unset ;
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*
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*/
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//printf("%x %x", status, (*(volatile unsigned long *) (SD_BASE+0x48)));
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//printf("%x %x", status, MCI_STATUS);
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//while(!button_read_device());
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//while(button_read_device());
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(*(volatile unsigned long *) (SD_BASE+0x0)) |= 0x10; // ?
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MCI_CTRL |= 0x10; // ?
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}
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static bool send_cmd(const int cmd, const int arg, const int flags,
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@ -288,23 +285,23 @@ static bool send_cmd(const int cmd, const int arg, const int flags,
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else if(cmd == 25) /* w */
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val |= 0x2700;
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int tmp = (*(volatile unsigned long *) (SD_BASE+0x10));
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(*(volatile unsigned long *) (SD_BASE+0x10)) = 0;
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int tmp = MCI_CLKENA;
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MCI_CLKENA = 0;
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MCI_COMMAND = 0x80202000;
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MCI_ARGUMENT = 0;
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int max = 10;
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while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE);
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(*(volatile unsigned long *) (SD_BASE+0x08)) &= ~0xff;
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(*(volatile unsigned long *) (SD_BASE+0x08)) |= 0;
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MCI_CLKDIV &= ~0xff;
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MCI_CLKDIV |= 0;
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MCI_COMMAND = 0x80202000;
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MCI_ARGUMENT = 0;
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max = 10;
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while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE);
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(*(volatile unsigned long *) (SD_BASE+0x10)) = tmp;
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MCI_CLKENA = tmp;
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MCI_COMMAND = 0x80202000;
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MCI_ARGUMENT = 0;
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@ -316,7 +313,7 @@ static bool send_cmd(const int cmd, const int arg, const int flags,
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MCI_ARGUMENT = arg;
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MCI_COMMAND = val;
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(*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x10;
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MCI_CTRL |= 0x10;
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max = 1000;
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while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */
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@ -412,8 +409,8 @@ static int sd_init_card(void)
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if(!send_cmd(SD_SET_BUS_WIDTH, card_info.rca | 2, MCI_NO_RESP, NULL))
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return -11;
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(*(volatile unsigned long *) (SD_BASE+0x18)) &= ~(0x10001);
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(*(volatile unsigned long *) (SD_BASE+0x18)) |= 0x1;
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MCI_CTYPE &= ~(0x10001);
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MCI_CTYPE |= 0x1;
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if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL))
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return -9;
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@ -474,36 +471,36 @@ static void sd_thread(void)
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static void init_controller(void)
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{
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int tmp = (*(volatile unsigned long *) (SD_BASE+0x70));
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int tmp = MCI_HCON;
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int shift = 1 + ((tmp << 26) >> 27);
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(*(volatile unsigned long *) (SD_BASE+0x04)) &= ~((1 << shift) -1);
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(*(volatile unsigned long *) (SD_BASE+0x04)) = (1 << shift) -1;
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MCI_PWREN &= ~((1 << shift) -1);
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MCI_PWREN = (1 << shift) -1;
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mci_delay();
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(*(volatile unsigned long *) (SD_BASE+0x00)) |= 1;
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MCI_CTRL |= 1;
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int max = 1000;
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while(max-- && !(*(volatile unsigned long *) (SD_BASE+0x00)) & 1)
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while(max-- && !(MCI_CTRL & 1))
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;
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MCI_CLEAR = 0xffffffff;
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MCI_RAW_STATUS = 0xffffffff;
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MCI_MASK = 0xffffbffe;
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(*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x10;
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(*(volatile unsigned long *) (SD_BASE+0x14)) = 0xffffffff;
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MCI_CTRL |= 0x10;
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MCI_TMOUT = 0xffffffff;
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(*(volatile unsigned long *) (SD_BASE+0x10)) = (1<<shift) - 1;
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MCI_CLKENA = (1<<shift) - 1;
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MCI_ARGUMENT = 0;
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MCI_COMMAND = 0x80202000;
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max = 10;
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while(max-- && (MCI_COMMAND & (1<<31))) ;
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(*(volatile unsigned long *) (SD_BASE+0x64)) = 0xfffff;
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MCI_DEBNCE = 0xfffff;
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(*(volatile unsigned long *) (SD_BASE+0x4c)) = ~0x7fff0fff; // interrupt mask ?
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(*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x503f0080;
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MCI_FIFOTH = ~0x7fff0fff;
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MCI_FIFOTH |= 0x503f0080;
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MCI_MASK = 0xffffbffe;
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}
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@ -657,20 +654,20 @@ static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool w
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write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
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(*(volatile unsigned long *) (SD_BASE+0x00)) |= 2;
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while(( *(volatile unsigned long *) (SD_BASE+0x00)) & 2) ;
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MCI_CTRL |= 2;
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while(MCI_CTRL & 2) ;
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//(*(volatile unsigned long *) (SD_BASE+0x1c)) = 512;
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(*(volatile unsigned long *) (SD_BASE+0x20)) = transfer * 512;
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//MCI_BLKSIZ = 512;
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MCI_BYTCNT = transfer * 512;
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(*(volatile unsigned long *) (SD_BASE+0x00)) |= 2;
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while(( *(volatile unsigned long *) (SD_BASE+0x00)) & 2) ;
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MCI_CTRL |= 2;
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while(MCI_CTRL & 2) ;
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(*(volatile unsigned long *) (SD_BASE+0x4c)) &= ~0x7fff0fff;
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MCI_FIFOTH &= ~0x7fff0fff;
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(*(volatile unsigned long *) (SD_BASE+0x00)) |= 0x20;
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MCI_CTRL |= 0x20;
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MCI_MASK = 0xBE8C;
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(*(volatile unsigned long *) (SD_BASE+0x4c)) |= 0x503f0080;
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MCI_FIFOTH |= 0x503f0080;
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if(card_info.ocr & (1<<30) ) /* SDHC */
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