forked from len0rd/rockbox
Apply Akio Idehara's fix for FS#7972 - Fix ARM's swp (xchg) inline assembly for gcc 4.2. Also avoids UNPREDICTABLE behavior that GCC should have always warned about.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15157 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
parent
fc43b9df82
commit
4829f7835a
1 changed files with 3 additions and 3 deletions
|
|
@ -372,7 +372,7 @@ struct core_entry
|
||||||
({ uint32_t o; \
|
({ uint32_t o; \
|
||||||
asm volatile( \
|
asm volatile( \
|
||||||
"swpb %0, %1, [%2]" \
|
"swpb %0, %1, [%2]" \
|
||||||
: "=r"(o) \
|
: "=&r"(o) \
|
||||||
: "r"(v), \
|
: "r"(v), \
|
||||||
"r"((uint8_t*)(a))); \
|
"r"((uint8_t*)(a))); \
|
||||||
o; })
|
o; })
|
||||||
|
|
@ -381,7 +381,7 @@ struct core_entry
|
||||||
({ uint32_t o; \
|
({ uint32_t o; \
|
||||||
asm volatile( \
|
asm volatile( \
|
||||||
"swp %0, %1, [%2]" \
|
"swp %0, %1, [%2]" \
|
||||||
: "=r"(o) \
|
: "=&r"(o) \
|
||||||
: "r"((uint32_t)(v)), \
|
: "r"((uint32_t)(v)), \
|
||||||
"r"((uint32_t*)(a))); \
|
"r"((uint32_t*)(a))); \
|
||||||
o; })
|
o; })
|
||||||
|
|
@ -390,7 +390,7 @@ struct core_entry
|
||||||
({ typeof (*(a)) o; \
|
({ typeof (*(a)) o; \
|
||||||
asm volatile( \
|
asm volatile( \
|
||||||
"swp %0, %1, [%2]" \
|
"swp %0, %1, [%2]" \
|
||||||
: "=r"(o) \
|
: "=&r"(o) \
|
||||||
: "r"(v), "r"(a)); \
|
: "r"(v), "r"(a)); \
|
||||||
o; })
|
o; })
|
||||||
#endif /* locking selection */
|
#endif /* locking selection */
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue