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Bus controller inits are valid for all models. Corrected WCR1 init according to the datasheet (dontcare bits shall be written as 1)

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5256 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2004-10-12 09:09:16 +00:00
parent ae815a0272
commit 4690ddd87a
1 changed files with 2 additions and 6 deletions
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8
firmware/system.c
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@ -492,13 +492,9 @@ void system_init(void)
BCR |= 0x2000; BCR |= 0x2000;
/* Bus state controller initializations. These are only necessary when /* Bus state controller initializations. These are only necessary when
running from flash. The correct settings for player models are not running from flash. */
verified, so we only do this for the recorder and for the Ondio. */ WCR1 = 0x40FD; /* Long wait states for CS6 (ATA), short for the rest. */
#if defined(HAVE_RECORDING) || defined(HAVE_MMC)
WCR1 = 0x4000; /* Long wait states for CS6 (ATA), short for the rest. */
WCR3 = 0x8000; /* WAIT is pulled up, 1 state inserted for CS6 */ WCR3 = 0x8000; /* WAIT is pulled up, 1 state inserted for CS6 */
#endif
} }
/* Utilize the user break controller to catch invalid memory accesses. */ /* Utilize the user break controller to catch invalid memory accesses. */