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Onda VX747:

Browse source 
* Add preliminary keymap
 * Split up generic MIPS stuff from Ingenic specific
 * Make apps/ compilable
 * Add SD driver
 * Fix RTC driver
 * Add debug screen
 * Other cleanups/rewrites/fixes


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19993 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2009-02-13 00:45:49 +00:00
parent c16e563aef
commit 4532d145f1
20 changed files with 1246 additions and 538 deletions
Download patch file Download diff file Expand all files Collapse all files

61
apps/keymaps/keymap-ondavx747.c Normal file
View file

@ -0,0 +1,61 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2009 by Maurus Cuelenaere
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
/* Button Code Definitions for the Onda VX747 target */
/* NB: Up/Down/Left/Right are not physical buttons - touchscreen emulation */
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "config.h"
#include "action.h"
#include "button.h"
#include "settings.h"
/*
* The format of the list is as follows
* { Action Code, Button code, Prereq button code }
* if there's no need to check the previous button's value, use BUTTON_NONE
* Insert LAST_ITEM_IN_LIST at the end of each mapping
*/
/*TODO*/
static const struct button_mapping button_context_standard[] = {
{ ACTION_STD_PREV, BUTTON_VOL_DOWN, BUTTON_NONE },
{ ACTION_STD_PREVREPEAT, BUTTON_VOL_DOWN|BUTTON_REPEAT, BUTTON_NONE },
{ ACTION_STD_NEXT, BUTTON_VOL_UP, BUTTON_NONE },
{ ACTION_STD_NEXTREPEAT, BUTTON_VOL_UP|BUTTON_REPEAT, BUTTON_NONE },
{ ACTION_STD_OK, BUTTON_MENU|BUTTON_REL, BUTTON_MENU },
{ ACTION_STD_CANCEL, BUTTON_POWER, BUTTON_NONE },
{ ACTION_STD_QUICKSCREEN, BUTTON_VOL_UP|BUTTON_REPEAT, BUTTON_NONE },
{ ACTION_STD_CONTEXT, BUTTON_MENU|BUTTON_REPEAT, BUTTON_NONE },
LAST_ITEM_IN_LIST
}; /* button_context_standard */
const struct button_mapping* target_get_context_mapping(int context)
{
(void)context;
return button_context_standard;
}

4
bootloader/ondavx747.c
View file

@ -101,7 +101,7 @@ static void boot_of(void)
int main(void)
{
int rc;
int rc, dummy;
void (*kernel_entry)(void);
kernel_init();
@ -114,7 +114,7 @@ int main(void)
reset_screen();
#ifdef HAVE_TOUCHSCREEN
rc = button_read_device(NULL);
rc = button_read_device(&dummy);
#else
rc = button_read_device();
#endif

6
firmware/common/timefuncs.c
View file

@ -104,10 +104,13 @@ int set_time(const struct tm *tm)
{
#if CONFIG_RTC
int rc;
#if CONFIG_RTC != RTC_JZ47XX
char rtcbuf[7];
#endif
if (valid_time(tm))
{
#if CONFIG_RTC != RTC_JZ47XX
rtcbuf[0]=((tm->tm_sec/10) << 4) | (tm->tm_sec%10);
rtcbuf[1]=((tm->tm_min/10) << 4) | (tm->tm_min%10);
rtcbuf[2]=((tm->tm_hour/10) << 4) | (tm->tm_hour%10);
@ -122,6 +125,9 @@ int set_time(const struct tm *tm)
#endif
rc = rtc_write_datetime(rtcbuf);
#else
rc = rtc_write_datetime((unsigned char*)tm);
#endif
if (rc < 0)
return -1;

34
firmware/drivers/rtc/rtc_jz4740.c
View file

@ -28,11 +28,7 @@
#include "jz4740.h"
#include "rtc.h"
#include "timefuncs.h"
static unsigned int epoch = 1900;
static const unsigned char days_in_mo[] = {
0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
#include "logf.h"
static const unsigned int yearday[5] = {0, 366, 366+365, 366+365*2, 366+365*3};
static const unsigned int sweekday = 6;
@ -52,8 +48,8 @@ static const unsigned int sum_monthday[13] = {
365
};
#if 0
static unsigned int jz_mktime(int year, int mon, int day, int hour, int min, int sec)
static unsigned int jz_mktime(int year, int mon, int day, int hour, int min,
int sec)
{
unsigned int seccounter;
@ -79,10 +75,9 @@ static unsigned int jz_mktime(int year, int mon, int day, int hour, int min, int
return seccounter;
}
#endif
static void jz_gettime(unsigned int rtc, int *year, int *mon, int *day, int *hour,
int *min, int *sec, int *weekday)
static void jz_gettime(unsigned int rtc, int *year, int *mon, int *day,
int *hour, int *min, int *sec, int *weekday)
{
unsigned int tday, tsec, i, tmp;
@ -143,9 +138,9 @@ int rtc_read_datetime(unsigned char* buf)
rtc_tm.tm_wday = wday;
/* Don't use centry, but start from year 1970 */
rtc_tm.tm_mon = mon;
if ((year += (epoch - 1900)) <= 69)
if (year <= 69)
year += 100;
rtc_tm.tm_year = year + 1900;
rtc_tm.tm_year = year;
rtc_tm.tm_yday = 0; /* Not implemented for now */
rtc_tm.tm_isdst = -1; /* Not implemented for now */
@ -156,7 +151,20 @@ int rtc_read_datetime(unsigned char* buf)
int rtc_write_datetime(unsigned char* buf)
{
(void)buf;
struct tm *rtc_tm = (struct tm*)buf;
unsigned int year, lval;
year = rtc_tm->tm_year;
/* Don't use centry, but start from year 1970 */
if (year > 69)
year -= 100;
year += 2000;
lval = jz_mktime(year, rtc_tm->tm_mon, rtc_tm->tm_mday, rtc_tm->tm_hour,
rtc_tm->tm_min, rtc_tm->tm_sec);
REG_RTC_RSR = lval;
return 0;
}
#if 0

891
firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
View file

File diff suppressed because it is too large Load diff

17
firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
View file

@ -22,6 +22,23 @@
#include "config.h"
#include "jz4740.h"
#include "system.h"
#include "audiohw.h"
/* TODO */
const struct sound_settings_info audiohw_settings[] = {
[SOUND_VOLUME] = {"dB", 0, 1, -73, 6, -20},
/* HAVE_SW_TONE_CONTROLS */
[SOUND_BASS] = {"dB", 0, 1, -24, 24, 0},
[SOUND_TREBLE] = {"dB", 0, 1, -24, 24, 0},
[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
#ifdef HAVE_RECORDING
[SOUND_LEFT_GAIN] = {"dB", 1, 1, 0, 31, 23},
[SOUND_RIGHT_GAIN] = {"dB", 1, 1, 0, 31, 23},
[SOUND_MIC_GAIN] = {"dB", 1, 1, 0, 1, 1},
#endif
};
static unsigned short codec_volume;
static unsigned short codec_base_gain;

65
firmware/target/mips/ingenic_jz47xx/crt0.S
View file

@ -43,14 +43,16 @@
.set mips32
.extern system_main
.extern main
.global _start
.global _start
.section .init.text
.set noreorder
.set noat
#ifdef BOOTLOADER
.word 0 /* Unknown */
/* These will get filled in scramble */
.word 0 /* Unknown */
.word 0 /* Filesize */
/* Relocate bootloader */
@ -64,12 +66,12 @@ _relocate_loop:
bne t1, t2, _relocate_loop
addiu t0, 4
#endif
_start:
la ra, _start
/*
----------------------------------------------------
init cp0 registers.
Init CP0 registers.
----------------------------------------------------
*/
mtc0 zero, C0_WATCHLO
@ -90,21 +92,21 @@ _start:
/*
----------------------------------------------------
init caches, assumes a 4way*128set*32byte i/d cache
Init caches, assumes a 4way*128set*32byte I/D cache
----------------------------------------------------
*/
li t0, 3 // enable cache for kseg0 accesses
mtc0 t0, C0_CONFIG // CONFIG reg
la t0, 0x80000000 // an idx op should use an unmappable address
ori t1, t0, 0x4000 // 16kB cache
mtc0 zero, C0_TAGLO // TAGLO reg
mtc0 zero, C0_TAGHI // TAGHI reg
li t0, 3 # enable cache for kseg0 accesses
mtc0 t0, C0_CONFIG # CONFIG reg
la t0, 0x80000000 # an idx op should use an unmappable address
ori t1, t0, 0x4000 # 16kB cache
mtc0 zero, C0_TAGLO # TAGLO reg
mtc0 zero, C0_TAGHI # TAGHI reg
_init_cache_loop:
cache 0x8, 0(t0) // index store icache tag
cache 0x9, 0(t0) // index store dcache tag
cache 0x8, 0(t0) # index store icache tag
cache 0x9, 0(t0) # index store dcache tag
bne t0, t1, _init_cache_loop
addiu t0, t0, 0x20 // 32 bytes per cache line
addiu t0, t0, 0x20 # 32 bytes per cache line
nop
/*
@ -120,7 +122,7 @@ _init_cache_loop:
/*
----------------------------------------------------
clear BSS section
Clear BSS section
----------------------------------------------------
*/
la t0, _edata
@ -132,7 +134,7 @@ _init_bss_loop:
/*
----------------------------------------------------
clear IBSS section
Clear IBSS section
----------------------------------------------------
*/
la t0, _iedata
@ -144,7 +146,7 @@ _init_ibss_loop:
/*
----------------------------------------------------
copy IRAM section
Copy IRAM section
----------------------------------------------------
*/
la t0, _iramcopy
@ -159,7 +161,7 @@ _init_iram_loop:
/*
----------------------------------------------------
setup stack, jump to C code
Setup stack
----------------------------------------------------
*/
la sp, stackend
@ -171,7 +173,15 @@ _init_stack_loop:
bne t0, sp, _init_stack_loop
addiu t0, t0, 4
la t0, system_main
/*
----------------------------------------------------
Jump to C code
----------------------------------------------------
*/
la t0, system_main /* Init clocks etc first */
jalr t0
nop
la t0, main
jr t0
nop
@ -182,11 +192,10 @@ _init_stack_loop:
* 0x180 - Exception/Interrupt handler
* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE)
*/
.section .vectors.1, "ax", %progbits
la k0, tlb_refill_handler
jr k0
la k0, tlb_refill_handler
jr k0
nop
.section .vectors.2, "ax", %progbits
@ -235,10 +244,10 @@ real_exception_handler:
sw v1, 0x64(sp)
sw v0, 0x68(sp)
sw $1, 0x6C(sp)
mflo k0 # Move From LO
mflo k0
nop
sw k0, 0x70(sp)
mfhi k0 # Move From HI
mfhi k0
nop
sw k0, 0x74(sp)
mfc0 k0, C0_STATUS # Status register
@ -294,10 +303,10 @@ _int:
lw v0, 0x68(sp)
lw $1, 0x6C(sp)
lw k0, 0x70(sp)
mtlo k0 # Move To LO
mtlo k0
nop
lw k0, 0x74(sp)
mthi k0 # Move To HI
mthi k0
nop
lw k0, 0x78(sp)
nop
@ -360,10 +369,10 @@ _exception:
lw v0, 0x68(sp)
lw $1, 0x6C(sp)
lw k0, 0x70(sp)
mtlo k0 # Move To LO
mtlo k0
nop
lw k0, 0x74(sp)
mthi k0 # Move To HI
mthi k0
nop
lw k0, 0x78(sp)
nop

39
firmware/target/mips/ingenic_jz47xx/debug-jz4740.c
View file

@ -21,6 +21,29 @@
#include "config.h"
#include "jz4740.h"
#include "debug-target.h"
#include <stdarg.h>
#include <stdio.h>
#include "lcd.h"
#include "kernel.h"
#include "font.h"
#include "button.h"
static int line = 0;
static void printf(const char *format, ...)
{
int len;
unsigned char *ptr;
char printfbuf[256];
va_list ap;
va_start(ap, format);
ptr = printfbuf;
len = vsnprintf(ptr, sizeof(printfbuf), format, ap);
va_end(ap);
lcd_puts(0, line++, ptr);
}
/*
* Clock Generation Module
@ -126,6 +149,20 @@ bool __dbg_ports(void)
bool __dbg_hw_info(void)
{
return false;
int btn = 0, touch;
lcd_setfont(FONT_SYSFIXED);
while(btn ^ BUTTON_POWER)
{
lcd_clear_display();
line = 0;
display_clocks();
display_enabled_clocks();
btn = button_read_device(&touch);
printf("X: %d Y: %d BTN: 0x%X", touch>>16, touch&0xFFFF, btn);
lcd_update();
sleep(HZ/16);
}
return true;
}

28
firmware/target/mips/ingenic_jz47xx/debug-target.h Normal file
View file

@ -0,0 +1,28 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2009 by Maurus Cuelenaere
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __DEBUG_TARGET_H_
#define __DEBUG_TARGET_H_
bool __dbg_hw_info(void);
bool __dbg_ports(void);
#endif /* __DEBUG_TARGET_H_ */

14
firmware/target/mips/ingenic_jz47xx/onda_vx747/ata-sd-target.h
View file

@ -38,16 +38,20 @@ int _sd_read_sectors(unsigned long start, int count, void* buf);
int _sd_write_sectors(unsigned long start, int count, const void* buf);
int _sd_init(void);
#define MMC_CD_PIN (29 + 1 * 32) /* Pin to check card insertion */
#define MMC_CD_PIN (32*1 + 29) /* Pin to check card insertion */
#define MSC_D0 (32*3 + 10)
#define MSC_D1 (32*3 + 11)
#define MSC_D2 (32*3 + 12)
#define MSC_CLK (32*3 + 9 )
static inline void mmc_init_gpio(void)
{
__gpio_as_msc();
__gpio_as_input(MMC_CD_PIN);
//__gpio_enable_pull(32*3+29);
__gpio_enable_pull(32*3+10);
__gpio_enable_pull(32*3+11);
__gpio_enable_pull(32*3+12);
__gpio_enable_pull(MSC_CLK);
__gpio_enable_pull(MSC_D0);
__gpio_enable_pull(MSC_D1);
__gpio_enable_pull(MSC_D2);
}
#endif

10
firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
View file

@ -35,7 +35,7 @@ static bool backlight_on;
static void set_backlight(int val)
{
(void)val;
(void)val;
}
bool _backlight_init(void)
@ -153,3 +153,11 @@ void _backlight_set_brightness(int brightness)
set_backlight(brightness);
}
#endif
#ifdef HAVE_LCD_SLEEP
/* Turn off LED supply */
void _backlight_lcd_sleep(void)
{
set_backlight_off();
}
#endif

2
firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h
View file

@ -29,10 +29,12 @@
#include <stdbool.h>
/*
bool _backlight_init(void);
void _backlight_on(void);
void _backlight_off(void);
void _backlight_set_brightness(int brightness);
bool backlight_enabled(void);
*/
#endif /* BACKLIGHT_TARGET_H */

13
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
View file

@ -26,6 +26,7 @@
#define PIN_CS_N (32*1+17) /* Chip select */
#define PIN_RESET_N (32*1+18) /* Reset */
#define LCD_PCLK (20000000) /* LCD PCLK */
#define my__gpio_as_lcd_16bit() \
do { \
@ -199,16 +200,15 @@ static void _set_lcd_bus(void)
static void _set_lcd_clock(void)
{
unsigned int val;
int pll_div;
__cpm_stop_lcd();
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source, 0:pllout/2 1: pllout */
pll_div = pll_div ? 1 : 2;
val = ( __cpm_get_pllout()/pll_div ) / __cpm_get_pclk();
val = __cpm_get_pllout2() / LCD_PCLK;
val--;
if ( val > 0x1ff )
val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */
__cpm_set_pixdiv(val);
__cpm_start_lcd();
}
@ -277,3 +277,8 @@ void lcd_off(void)
{
_display_off();
}
void lcd_set_contrast(int val)
{
(void)val;
}

5
firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c
View file

@ -42,3 +42,8 @@ void power_init(void)
{
__gpio_as_input(USB_CHARGER_GPIO);
}
bool charging_state(void)
{
return false;
}

93
firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
View file

@ -26,6 +26,8 @@
#include "button-target.h"
#include "powermgmt.h"
#include "kernel.h"
#include "backlight.h"
#include "logf.h"
#ifdef ONDA_VX747
#define BTN_OFF (1 << 29)
@ -54,15 +56,16 @@
(2 << SADC_CFG_CLKOUT_NUM_BIT) | \
SADC_CFG_XYZ1Z2 | \
SADC_CFG_SNUM | \
(2 << SADC_CFG_CLKDIV_BIT) | \
(1 << SADC_CFG_CLKDIV_BIT) | \
SADC_CFG_PBAT_HIGH | \
SADC_CFG_CMD_INT_PEN \
)
static signed int x_pos, y_pos;
static int datacount = 0, cur_touch = 0;
static bool pen_down = false;
static volatile unsigned short bat_val = 0;
static int datacount = 0;
static volatile int cur_touch = 0;
static volatile bool pen_down = false;
static volatile unsigned short bat_val;
static struct mutex battery_mtx;
static enum touchscreen_mode current_mode = TOUCHSCREEN_POINT;
@ -76,20 +79,20 @@ static const int touchscreen_buttons[3][3] =
const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
{
/* TODO */
3400
1400
};
const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] =
{
/* TODO */
3300
1300
};
/* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */
const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] =
{
/* TODO */
{ 3300, 3680, 3740, 3760, 3780, 3810, 3870, 3930, 3970, 4070, 4160 },
{ 1300, 3680, 3740, 3760, 3780, 3810, 3870, 3930, 3970, 4070, 4160 },
};
/* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */
@ -105,23 +108,34 @@ const unsigned short percent_to_volt_charge[11] =
/* Returns battery voltage from ADC [millivolts] */
unsigned int battery_adc_voltage(void)
{
register unsigned short dummy;
unsigned int val, i;
mutex_lock(&battery_mtx);
dummy = REG_SADC_BATDAT;
dummy = REG_SADC_BATDAT;
val = REG_SADC_BATDAT;
val = REG_SADC_BATDAT;
bat_val = 0;
REG_SADC_ENA |= SADC_ENA_PBATEN;
for(i=0; i<4; i++)
{
bat_val = 0;
/* primitive wakeup event */
while(bat_val == 0)
sleep(0);
val += bat_val;
}
REG_SADC_ENA &= ~SADC_ENA_PBATEN;
/* primitive wakeup event */
while(bat_val == 0)
yield();
val /= 4;
logf("%d %d %d", val, (val*BATTERY_SCALE_FACTOR)>>12,
(val*0xAAAAAAAB >> 32) >> 1);
mutex_unlock(&battery_mtx);
return (bat_val*BATTERY_SCALE_FACTOR)>>12;
return (val*BATTERY_SCALE_FACTOR)>>12;
}
void button_init_device(void)
@ -135,11 +149,11 @@ void button_init_device(void)
system_enable_irq(IRQ_SADC);
REG_SADC_SAMETIME = 350;
REG_SADC_SAMETIME = 10;
REG_SADC_WAITTIME = 100;
REG_SADC_STATE &= (~REG_SADC_STATE);
REG_SADC_CTRL = (~(SADC_CTRL_PENDM | SADC_CTRL_PENUM | SADC_CTRL_TSRDYM | SADC_CTRL_PBATRDYM));
REG_SADC_ENA = (SADC_ENA_TSEN | SADC_ENA_PBATEN);
REG_SADC_ENA = SADC_ENA_TSEN;
#ifdef ONDA_VX747
__gpio_as_input(32*3 + 29);
@ -213,19 +227,24 @@ int button_read_device(int *data)
if(tmp & BTN_OFF)
ret |= BUTTON_POWER;
if(current_mode == TOUCHSCREEN_BUTTON && cur_touch != 0)
if(cur_touch != 0)
{
int px_x = cur_touch >> 16;
int px_y = cur_touch & 0xFFFF;
ret |= touchscreen_buttons[px_y/(LCD_HEIGHT/3)]
[px_x/(LCD_WIDTH/3)];
}
else if(pen_down)
{
ret |= BUTTON_TOUCH;
if(data != NULL && cur_touch != 0)
if(current_mode == TOUCHSCREEN_BUTTON)
{
int px_x = cur_touch >> 16;
int px_y = cur_touch & 0xFFFF;
ret |= touchscreen_buttons[px_y/(LCD_HEIGHT/3)]
[px_x/(LCD_WIDTH/3)];
}
else if(pen_down)
{
ret |= BUTTON_TOUCHSCREEN;
*data = cur_touch;
}
}
if(ret & BUTTON_TOUCHSCREEN && !is_backlight_on(true))
*data = 0;
return ret;
}
@ -299,15 +318,17 @@ void SADC(void)
x_pos += xData;
y_pos += yData;
}
datacount++;
if(datacount >= TS_AD_COUNT)
{
cur_touch = touch_to_pixels(x_pos/datacount, y_pos/datacount);
datacount = 0;
}
}
datacount++;
if(datacount >= TS_AD_COUNT)
{
cur_touch = touch_to_pixels(x_pos/datacount, y_pos/datacount);
else
datacount = 0;
}
}
if(state & SADC_CTRL_PBATRDYM)
@ -316,3 +337,7 @@ void SADC(void)
/* Battery AD IRQ */
}
}
void adc_init(void)
{
}

3
firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
View file

@ -113,7 +113,8 @@ size_t pcm_get_bytes_waiting(void)
const void * pcm_play_dma_get_peak_buffer(int *count)
{
/* TODO */
*count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL)>>2;
//*count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL)>>2;
*count = 0;
return NULL;
}

351
firmware/target/mips/ingenic_jz47xx/system-jz4740.c
View file

@ -22,11 +22,9 @@
#include "config.h"
#include "jz4740.h"
#include "mips.h"
#include "mipsregs.h"
#include "mmu-mips.h"
#include "panic.h"
#include "system.h"
#include "string.h"
#include "kernel.h"
#define NUM_DMA 6
@ -36,165 +34,40 @@
static int irq;
static void UIRQ(void)
{
panicf("Unhandled interrupt occurred: %d\n", irq);
panicf("Unhandled interrupt occurred: %d", irq);
}
#define default_interrupt(name) \
extern __attribute__((weak,alias("UIRQ"))) void name (void)
#define intr(name) extern __attribute__((weak,alias("UIRQ"))) void name (void)
default_interrupt(I2C);
default_interrupt(EMC);
default_interrupt(UHC);
default_interrupt(UART0);
default_interrupt(SADC);
default_interrupt(MSC);
default_interrupt(RTC);
default_interrupt(SSI);
default_interrupt(CIM);
default_interrupt(AIC);
default_interrupt(ETH);
default_interrupt(TCU2);
default_interrupt(TCU1);
default_interrupt(TCU0);
default_interrupt(UDC);
default_interrupt(IPU);
default_interrupt(LCD);
intr(I2C);intr(EMC);intr(UHC);intr(UART0);intr(SADC);intr(MSC);intr(RTC);
intr(SSI);intr(CIM);intr(AIC);intr(ETH);intr(TCU2);intr(TCU1);intr(TCU0);
intr(UDC);intr(IPU);intr(LCD);
default_interrupt(DMA0);
default_interrupt(DMA1);
default_interrupt(DMA2);
default_interrupt(DMA3);
default_interrupt(DMA4);
default_interrupt(DMA5);
intr(DMA0);intr(DMA1);intr(DMA2);intr(DMA3);intr(DMA4);intr(DMA5);
default_interrupt(GPIO0);
default_interrupt(GPIO1);
default_interrupt(GPIO2);
default_interrupt(GPIO3);
default_interrupt(GPIO4);
default_interrupt(GPIO5);
default_interrupt(GPIO6);
default_interrupt(GPIO7);
default_interrupt(GPIO8);
default_interrupt(GPIO9);
default_interrupt(GPIO10);
default_interrupt(GPIO11);
default_interrupt(GPIO12);
default_interrupt(GPIO13);
default_interrupt(GPIO14);
default_interrupt(GPIO15);
default_interrupt(GPIO16);
default_interrupt(GPIO17);
default_interrupt(GPIO18);
default_interrupt(GPIO19);
default_interrupt(GPIO20);
default_interrupt(GPIO21);
default_interrupt(GPIO22);
default_interrupt(GPIO23);
default_interrupt(GPIO24);
default_interrupt(GPIO25);
default_interrupt(GPIO26);
default_interrupt(GPIO27);
default_interrupt(GPIO28);
default_interrupt(GPIO29);
default_interrupt(GPIO30);
default_interrupt(GPIO31);
default_interrupt(GPIO32);
default_interrupt(GPIO33);
default_interrupt(GPIO34);
default_interrupt(GPIO35);
default_interrupt(GPIO36);
default_interrupt(GPIO37);
default_interrupt(GPIO38);
default_interrupt(GPIO39);
default_interrupt(GPIO40);
default_interrupt(GPIO41);
default_interrupt(GPIO42);
default_interrupt(GPIO43);
default_interrupt(GPIO44);
default_interrupt(GPIO45);
default_interrupt(GPIO46);
default_interrupt(GPIO47);
default_interrupt(GPIO48);
default_interrupt(GPIO49);
default_interrupt(GPIO50);
default_interrupt(GPIO51);
default_interrupt(GPIO52);
default_interrupt(GPIO53);
default_interrupt(GPIO54);
default_interrupt(GPIO55);
default_interrupt(GPIO56);
default_interrupt(GPIO57);
default_interrupt(GPIO58);
default_interrupt(GPIO59);
default_interrupt(GPIO60);
default_interrupt(GPIO61);
default_interrupt(GPIO62);
default_interrupt(GPIO63);
default_interrupt(GPIO64);
default_interrupt(GPIO65);
default_interrupt(GPIO66);
default_interrupt(GPIO67);
default_interrupt(GPIO68);
default_interrupt(GPIO69);
default_interrupt(GPIO70);
default_interrupt(GPIO71);
default_interrupt(GPIO72);
default_interrupt(GPIO73);
default_interrupt(GPIO74);
default_interrupt(GPIO75);
default_interrupt(GPIO76);
default_interrupt(GPIO77);
default_interrupt(GPIO78);
default_interrupt(GPIO79);
default_interrupt(GPIO80);
default_interrupt(GPIO81);
default_interrupt(GPIO82);
default_interrupt(GPIO83);
default_interrupt(GPIO84);
default_interrupt(GPIO85);
default_interrupt(GPIO86);
default_interrupt(GPIO87);
default_interrupt(GPIO88);
default_interrupt(GPIO89);
default_interrupt(GPIO90);
default_interrupt(GPIO91);
default_interrupt(GPIO92);
default_interrupt(GPIO93);
default_interrupt(GPIO94);
default_interrupt(GPIO95);
default_interrupt(GPIO96);
default_interrupt(GPIO97);
default_interrupt(GPIO98);
default_interrupt(GPIO99);
default_interrupt(GPIO100);
default_interrupt(GPIO101);
default_interrupt(GPIO102);
default_interrupt(GPIO103);
default_interrupt(GPIO104);
default_interrupt(GPIO105);
default_interrupt(GPIO106);
default_interrupt(GPIO107);
default_interrupt(GPIO108);
default_interrupt(GPIO109);
default_interrupt(GPIO110);
default_interrupt(GPIO111);
default_interrupt(GPIO112);
default_interrupt(GPIO113);
default_interrupt(GPIO114);
default_interrupt(GPIO115);
default_interrupt(GPIO116);
default_interrupt(GPIO117);
default_interrupt(GPIO118);
default_interrupt(GPIO119);
default_interrupt(GPIO120);
default_interrupt(GPIO121);
default_interrupt(GPIO122);
default_interrupt(GPIO123);
default_interrupt(GPIO124);
default_interrupt(GPIO125);
default_interrupt(GPIO126);
default_interrupt(GPIO127);
intr(GPIO0);intr(GPIO1);intr(GPIO2);intr(GPIO3);intr(GPIO4);intr(GPIO5);
intr(GPIO6);intr(GPIO7);intr(GPIO8);intr(GPIO9);intr(GPIO10);intr(GPIO11);
intr(GPIO12);intr(GPIO13);intr(GPIO14);intr(GPIO15);intr(GPIO16);intr(GPIO17);
intr(GPIO18);intr(GPIO19);intr(GPIO20);intr(GPIO21);intr(GPIO22);intr(GPIO23);
intr(GPIO24);intr(GPIO25);intr(GPIO26);intr(GPIO27);intr(GPIO28);intr(GPIO29);
intr(GPIO30);intr(GPIO31);intr(GPIO32);intr(GPIO33);intr(GPIO34);intr(GPIO35);
intr(GPIO36);intr(GPIO37);intr(GPIO38);intr(GPIO39);intr(GPIO40);intr(GPIO41);
intr(GPIO42);intr(GPIO43);intr(GPIO44);intr(GPIO45);intr(GPIO46);intr(GPIO47);
intr(GPIO48);intr(GPIO49);intr(GPIO50);intr(GPIO51);intr(GPIO52);intr(GPIO53);
intr(GPIO54);intr(GPIO55);intr(GPIO56);intr(GPIO57);intr(GPIO58);intr(GPIO59);
intr(GPIO60);intr(GPIO61);intr(GPIO62);intr(GPIO63);intr(GPIO64);intr(GPIO65);
intr(GPIO66);intr(GPIO67);intr(GPIO68);intr(GPIO69);intr(GPIO70);intr(GPIO71);
intr(GPIO72);intr(GPIO73);intr(GPIO74);intr(GPIO75);intr(GPIO76);intr(GPIO77);
intr(GPIO78);intr(GPIO79);intr(GPIO80);intr(GPIO81);intr(GPIO82);intr(GPIO83);
intr(GPIO84);intr(GPIO85);intr(GPIO86);intr(GPIO87);intr(GPIO88);intr(GPIO89);
intr(GPIO90);intr(GPIO91);intr(GPIO92);intr(GPIO93);intr(GPIO94);intr(GPIO95);
intr(GPIO96);intr(GPIO97);intr(GPIO98);intr(GPIO99);intr(GPIO100);intr(GPIO101);
intr(GPIO102);intr(GPIO103);intr(GPIO104);intr(GPIO105);intr(GPIO106);
intr(GPIO107);intr(GPIO108);intr(GPIO109);intr(GPIO110);intr(GPIO111);
intr(GPIO112);intr(GPIO113);intr(GPIO114);intr(GPIO115);intr(GPIO116);
intr(GPIO117);intr(GPIO118);intr(GPIO119);intr(GPIO120);intr(GPIO121);
intr(GPIO122);intr(GPIO123);intr(GPIO124);intr(GPIO125);intr(GPIO126);
intr(GPIO127);
static void (* const irqvector[])(void) =
{
@ -281,17 +154,16 @@ static void ack_irq(unsigned int irq)
__intc_ack_irq(irq);
}
static unsigned long ipl;
static int get_irq_number(void)
{
register int irq = 0;
static unsigned long ipl;
register int irq;
ipl |= REG_INTC_IPR;
if (ipl == 0)
return -1;
/* find out the real irq defined in irq_xxx.c */
for (irq = 31; irq >= 0; irq--)
if (ipl & (1 << irq))
break;
@ -369,15 +241,14 @@ void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr);
}
static unsigned int iclk;
static void detect_clock(void)
void tlb_refill_handler(void)
{
iclk = __cpm_get_cclk();
panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr());
}
void udelay(unsigned int usec)
{
unsigned int i = usec * (iclk / 2000000);
unsigned int i = usec * (__cpm_get_cclk() / 2000000);
__asm__ __volatile__ (
".set noreorder \n"
"1: \n"
@ -396,135 +267,6 @@ void mdelay(unsigned int msec)
udelay(1000);
}
/* Core-level interrupt masking */
void clear_interrupts(void)
{
register unsigned int t;
t = read_c0_status();
t &= ~1;
write_c0_status(t);
}
unsigned int mips_get_sr(void)
{
return read_c0_status();
}
void store_interrupts(void)
{
register unsigned int t;
t = read_c0_status();
t |= 1;
t &= ~2;
write_c0_status(t);
}
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
#define CACHE_SIZE 16*1024
#define CACHE_LINE_SIZE 32
#define KSEG0 0x80000000
#define SYNC_WB() __asm__ __volatile__ ("sync")
#define __CACHE_OP(op, addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips32\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder \n" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
void __flush_dcache_line(unsigned long addr)
{
__CACHE_OP(Hit_Writeback_Inv_D, addr);
SYNC_WB();
}
void __icache_invalidate_all(void)
{
unsigned int i;
asm volatile (".set noreorder \n"
".set mips32 \n"
"mtc0 $0, $28 \n" /* TagLo */
"mtc0 $0, $29 \n" /* TagHi */
".set mips0 \n"
".set reorder \n"
);
for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE)
__CACHE_OP(Index_Store_Tag_I, i);
/* invalidate btb */
asm volatile (
".set mips32 \n"
"mfc0 %0, $16, 7 \n"
"nop \n"
"ori %0, 2 \n"
"mtc0 %0, $16, 7 \n"
".set mips0 \n"
:
: "r" (i));
}
void __dcache_invalidate_all(void)
{
unsigned int i;
asm volatile (".set noreorder \n"
".set mips32 \n"
"mtc0 $0, $28 \n"
"mtc0 $0, $29 \n"
".set mips0 \n"
".set reorder \n"
);
for (i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE)
__CACHE_OP(Index_Store_Tag_D, i);
}
void __dcache_writeback_all(void)
{
unsigned int i;
for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE)
__CACHE_OP(Index_Writeback_Inv_D, i);
SYNC_WB();
}
void dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
if (size >= CACHE_SIZE)
__dcache_writeback_all();
else
{
unsigned long dc_lsize = CACHE_LINE_SIZE;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
for(; a < end; a += dc_lsize)
__flush_dcache_line(a); /* Hit_Writeback_Inv_D */
}
}
void tlb_refill_handler(void)
{
panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr());
}
static int dma_count = 0;
void dma_enable(void)
{
@ -718,9 +460,8 @@ static void sdram_init(void)
/* everything is ok now */
}
extern int main(void);
void system_main(void) ICODE_ATTR;
void system_main(void)
/* Gets called *before* main */
void ICODE_ATTR system_main(void)
{
int i;
@ -733,24 +474,16 @@ void system_main(void)
for(i=0; i<IRQ_MAX; i++)
dis_irq(i);
tlb_init();
//pll_init();
//sdram_init();
detect_clock();
mmu_init();
pll_init();
sdram_init();
/* Disable unneeded clocks, clocks are enabled when needed */
__cpm_stop_all();
__cpm_suspend_usbhost();
/* Enable interrupts at core level */
store_interrupts();
main(); /* Shouldn't return */
while(1)
core_idle();
enable_interrupt();
}
void system_reboot(void)
@ -781,8 +514,8 @@ void power_off(void)
__rtc_clear_hib_stat_all();
/* __rtc_set_scratch_pattern(0x12345678); */
__rtc_enable_alarm_wakeup();
__rtc_set_hrcr_val(0xfe0);
__rtc_set_hwfcr_val((0xFFFF << 4));
__rtc_set_hrcr_val(0xFE0);
__rtc_set_hwfcr_val(0xFFFF << 4);
__rtc_power_down();
while(1);

43
firmware/target/mips/ingenic_jz47xx/system-target.h
View file

@ -26,12 +26,11 @@
#include "jz4740.h"
#include "mipsregs.h"
#define CACHE_SIZE 16*1024
#define CACHE_LINE_SIZE 32
#include "mmu-mips.h"
/* This one returns the old status */
#define HIGHEST_IRQ_LEVEL 0
#define set_irq_level(status) \
set_interrupt_status((status), ST0_IE)
static inline int set_interrupt_status(int status, int mask)
{
unsigned int res, oldstatus;
@ -56,48 +55,32 @@ static inline void disable_interrupt(void)
clear_c0_status(ST0_IE);
}
#define disable_irq() \
disable_interrupt()
#define enable_irq() \
enable_interrupt()
static inline int disable_interrupt_save(int mask)
{
unsigned int oldstatus;
oldstatus = read_c0_status();
write_c0_status(oldstatus & ~mask);
return oldstatus;
return set_interrupt_status(0, mask);
}
#define disable_irq_save() \
disable_interrupt_save(ST0_IE)
static inline void restore_interrupt(int status)
{
write_c0_status(status);
}
#define restore_irq(c0_status) \
restore_interrupt(c0_status)
#define disable_irq() disable_interrupt()
#define enable_irq() enable_interrupt()
#define HIGHEST_IRQ_LEVEL 0
#define set_irq_level(status) set_interrupt_status((status), ST0_IE)
#define disable_irq_save() disable_interrupt_save(ST0_IE)
#define restore_irq(c0_status) restore_interrupt(c0_status)
#define swap16(x) (((x) & 0xff) << 8 | ((x) >> 8) & 0xff)
#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | \
((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
#define UNCACHED_ADDRESS(addr) ((unsigned int)(addr) | 0xA0000000)
#define UNCACHED_ADDR(x) UNCACHED_ADDRESS((x))
#define PHYSADDR(x) ((x) & 0x1fffffff)
void __dcache_writeback_all(void);
void __dcache_invalidate_all(void);
void __icache_invalidate_all(void);
void __flush_dcache_line(unsigned long addr);
void dma_cache_wback_inv(unsigned long addr, unsigned long size);
void system_enable_irq(unsigned int irq);
void store_interrupts(void);
void clear_interrupts(void);
void udelay(unsigned int usec);
void mdelay(unsigned int msec);
void power_off(void);

92
firmware/target/mips/mmu-mips.c
View file

@ -112,7 +112,7 @@ void map_address(unsigned long virtual, unsigned long physical,
add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK);
}
void tlb_init(void)
void mmu_init(void)
{
write_c0_pagemask(DEFAULT_PAGE_MASK);
write_c0_wired(0);
@ -124,3 +124,93 @@ void tlb_init(void)
map_address(0x80004000, 0x80004000, MEM * 0x100000, K_CacheAttrC);
*/
}
#define SYNC_WB() __asm__ __volatile__ ("sync")
#define __CACHE_OP(op, addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips32\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder \n" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
void __flush_dcache_line(unsigned long addr)
{
__CACHE_OP(DCHitWBInv, addr);
SYNC_WB();
}
void __icache_invalidate_all(void)
{
unsigned int i;
asm volatile (".set noreorder \n"
".set mips32 \n"
"mtc0 $0, $28 \n" /* TagLo */
"mtc0 $0, $29 \n" /* TagHi */
".set mips0 \n"
".set reorder \n"
);
for(i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHE_LINE_SIZE)
__CACHE_OP(ICIndexStTag, i);
/* invalidate btb */
asm volatile (
".set mips32 \n"
"mfc0 %0, $16, 7 \n"
"nop \n"
"ori %0, 2 \n"
"mtc0 %0, $16, 7 \n"
".set mips0 \n"
:
: "r" (i));
}
void cpucache_invalidate(void)
{
__icache_invalidate_all();
}
void __dcache_invalidate_all(void)
{
unsigned int i;
asm volatile (".set noreorder \n"
".set mips32 \n"
"mtc0 $0, $28 \n"
"mtc0 $0, $29 \n"
".set mips0 \n"
".set reorder \n"
);
for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHE_LINE_SIZE)
__CACHE_OP(DCIndexStTag, i);
}
void __dcache_writeback_all(void)
{
unsigned int i;
for(i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHE_LINE_SIZE)
__CACHE_OP(DCIndexWBInv, i);
SYNC_WB();
}
void dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
if (size >= CACHE_SIZE)
__dcache_writeback_all();
else
{
unsigned long dc_lsize = CACHE_LINE_SIZE;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
for(; a < end; a += dc_lsize)
__flush_dcache_line(a);
}
}

13
firmware/target/mips/mmu-mips.h
View file

@ -22,8 +22,19 @@
#ifndef __MMU_MIPS_INCLUDE_H
#define __MMU_MIPS_INCLUDE_H
#include "system-target.h"
void map_address(unsigned long virtual, unsigned long physical,
unsigned long length, unsigned int cache_flags);
void tlb_init(void);
void mmu_init(void);
#define HAVE_CPUCACHE_INVALIDATE
//#define HAVE_CPUCACHE_FLUSH
void __dcache_writeback_all(void);
void __dcache_invalidate_all(void);
void __icache_invalidate_all(void);
void __flush_dcache_line(unsigned long addr);
void dma_cache_wback_inv(unsigned long addr, unsigned long size);
#endif /* __MMU_MIPS_INCLUDE_H */