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TIMERB is in a different location on the S5L8701

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22716 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Dave Chapman 2009-09-17 08:05:19 +00:00
parent d67c4d2f6b
commit 43ec944e3c
3 changed files with 18 additions and 3 deletions
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5
firmware/export/s5l8700.h
View file

@ -125,6 +125,11 @@
#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */
#define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */
#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */
#if CONFIG_CPU==S5L8701
#define INTMSK_TIMERB (1<<5)
#else
#define INTMSK_TIMERB (1<<7)
#endif
#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */
#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */
#define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */

2
firmware/target/arm/s5l8700/kernel-s5l8700.c
View file

@ -54,6 +54,6 @@ void tick_start(unsigned int interval_in_ms)
TBCMD = (1 << 0); /* TB_EN */ TBCMD = (1 << 0); /* TB_EN */
/* enable timer interrupt */ /* enable timer interrupt */
INTMSK |= (1 << 7); INTMSK |= INTMSK_TIMERB;
} }

14
firmware/target/arm/s5l8700/system-s5l8700.c
View file

@ -66,7 +66,12 @@ default_interrupt(INT_ADC);
static void (* const irqvector[])(void) = static void (* const irqvector[])(void) =
{ {
EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB, EXT0,EXT1,EXT2,EINT_VBUS,EINTG,
#if CONFIG_CPU==S5L8701
INT_TIMERB,INT_WDT,INT_TIMERA,
#else
INT_TIMERA,INT_WDT,INT_TIMERB,
#endif
INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST, INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT, INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
@ -74,7 +79,12 @@ static void (* const irqvector[])(void) =
static const char * const irqname[] = static const char * const irqname[] =
{ {
"EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB", "EXT0","EXT1","EXT2","EINT_VBUS","EINTG",
#if CONFIG_CPU==S5L8701
"INT_TIMERB","INT_WDT","INT_TIMERA",
#else
"INT_TIMERA","INT_WDT","INT_TIMERB",
#endif
"INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST", "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT", "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
"INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC" "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"