forked from len0rd/rockbox
Implement set_cpu_frequency() for TCC780x, but leave it disabled for now as switching can cause an occasional freeze. Reduce default speed from maximum to 48Mhz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16882 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rob Purchase
parent
12b6c847c5
commit
3d36f4e938
3 changed files with 69 additions and 73 deletions
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@ -119,10 +119,10 @@
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#define HAVE_ATA_POWER_OFF
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/* Define this to the CPU frequency */
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#define CPU_FREQ 192000000
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#define CPU_FREQ 48000000
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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/* #define HAVE_ADJUSTABLE_CPU_FREQ */
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/* Offset ( in the firmware file's header ) to the file CRC */
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#define FIRMWARE_OFFSET_FILE_CRC 0
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@ -21,8 +21,8 @@
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#include "system-arm.h"
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#define CPUFREQ_DEFAULT 98784000
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#define CPUFREQ_NORMAL 98784000
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#define CPUFREQ_DEFAULT 32000000
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#define CPUFREQ_NORMAL 48000000
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#define CPUFREQ_MAX 192000000
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#define inl(a) (*(volatile unsigned long *) (a))
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@ -151,59 +151,6 @@ void fiq_handler(void)
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#endif /* !defined(BOOTLOADER) */
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/* TODO:
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a) this is not the place for this function
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b) it currently ignores the supplied frequency and uses default values
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c) if the PLL being set drives any PCKs, an appropriate new clock divider
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will have to be re-calculated for those PCKs (the OF maintains a list of
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PCK frequencies for this purpose).
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*/
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void set_pll_frequency(unsigned int pll_number, unsigned int frequency)
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{
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int i = 0;
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if (pll_number > 1) return;
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/* The frequency parameter is currently ignored and temporary values are
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used (PLL0=192Mhz, PLL1=216Mhz). The D2 firmware uses a lookup table
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to derive the values of PLLxCFG from a the supplied frequency.
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Presumably we will need to do something similar. */
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if (pll_number == 0)
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{
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/* drive CPU off Xin while switching */
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CLKCTRL = 0xB00FF014; /* Xin enable, Fsys driven by Xin, Fbus = Fsys,
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MCPU=Fbus, SCPU=Fbus */
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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PLL0CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 24); /* disable PLL0 divider */
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PLL0CFG = 0x80019808; /* set for 192Mhz (with power down) */
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PLL0CFG = PLL0CFG &~ (1<<31); /* power up */
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CLKCTRL = (CLKCTRL & ~0x1f) | 0x800FF010;
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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}
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else if (pll_number == 1)
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{
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PLL1CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 16); /* disable PLL1 divider */
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PLL1CFG = 0x80002503; /* set for 216Mhz (with power down)*/
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PLL1CFG = PLL1CFG &~ (1<<31); /* power up */
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}
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i = 0x1000;
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while (--i) {};
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}
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/* TODO - these should live in the target-specific directories and
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once we understand what all the GPIO pins do, move the init to the
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specific driver for that hardware. For now, we just perform the
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@ -242,7 +189,14 @@ static void clock_init(void)
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int i;
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CSCFG3 = (CSCFG3 &~ 0x3fff) | 0x841;
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CLKCTRL = (CLKCTRL & ~0xff) | 0x14;
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/* Enable Xin (12Mhz), Fsys = Xin, Fbus = Fsys/2, MCPU=Fsys, SCPU=Fsys */
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CLKCTRL = 0x800FF014;
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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PCLK_RFREQ = 0x1401002d; /* RAM refresh source = Xin (4) / 0x2d = 266kHz */
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@ -252,13 +206,27 @@ static void clock_init(void)
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MCFG1 |= 1;
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SDCFG1 = (SDCFG &~ 0x7000) | 0x2000;
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PLL0CFG |= 0x80000000; /* power down */
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PLL0CFG = 0x14010000; /* power up, source = Xin (4) undivided = 12Mhz */
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/* Configure PLL0 to 192Mhz, for CPU scaling */
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PLL0CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 24); /* disable PLL0 divider */
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PLL0CFG = 0x80019808; /* set for 192Mhz (with power down) */
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PLL0CFG = PLL0CFG &~ (1<<31); /* power up */
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/* Configure PLL1 to 216Mz, for LCD clock (when divided by 2) */
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PLL1CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 16); /* disable PLL1 divider */
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PLL1CFG = 0x80002503; /* set for 216Mhz (with power down)*/
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PLL1CFG = PLL1CFG &~ (1<<31); /* power up */
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i = 0x8000;
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while (--i) {};
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CLKCTRL = (CLKCTRL &~ 0x1f) | 0x800FF010; /* CPU and COP driven by PLL0 */
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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set_cpu_frequency(CPUFREQ_NORMAL);
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#else
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/* 48Mhz: Fsys = PLL0 (192Mhz) Fbus = Fsys/4 CPU = Fbus, COP = Fbus */
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CLKCTRL = (1<<31) | (3<<28) | (3<<4);
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#endif
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asm volatile (
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"nop \n\t"
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@ -274,8 +242,6 @@ static void clock_init(void)
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#ifdef COWON_D2
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void system_init(void)
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{
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int i;
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MBCFG = 0x19;
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if (TCC780_VER == 0)
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@ -296,6 +262,7 @@ void system_init(void)
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VCTRL |= (1<<31); /* Reading from VNIRQ clears that interrupt */
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/* Write IRQ priority registers using ints - a freeze occurs otherwise */
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int i;
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for (i = 0; i < 7; i++)
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{
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IRQ_PRIORITY_TABLE[i] = ((int*)irqpriority)[i];
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@ -307,33 +274,62 @@ void system_init(void)
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gpio_init();
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clock_init();
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/* TODO: these almost certainly shouldn't be here */
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set_pll_frequency(0, 192000000); /* drives CPU */
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set_pll_frequency(1, 216000000); /* drives LCD PXCLK - divided by 2 */
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}
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#endif
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void system_reboot(void)
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{
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#warning function not implemented
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SWRESET = -1;
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}
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int system_memory_guard(int newmode)
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{
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#warning function not implemented
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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/* Note: This is not currently enabled because switching seems to
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cause an occasional freeze. To be investigated. */
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void set_cpu_frequency(long frequency)
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{
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#warning function not implemented
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(void)frequency;
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/* CPU/COP frequencies can be scaled between Fbus (min) and Fsys (max).
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Fbus should not be set below ~32Mhz with LCD enabled or the display
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will be garbled. */
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if (frequency == CPUFREQ_MAX)
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{
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/* 192Mhz:
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Fsys = PLL0 (192Mhz)
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Fbus = Fsys/2
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CPU = Fsys, COP = Fsys */
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CLKCTRL = (1<<31) | (0xFF<<12) | (1<<4);
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}
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else if (frequency == CPUFREQ_NORMAL)
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{
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/* 48Mhz:
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Fsys = PLL0 (192Mhz)
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Fbus = Fsys/4
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CPU = Fbus, COP = Fbus */
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CLKCTRL = (1<<31) | (3<<28) | (3<<4);
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}
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else
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{
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/* 32Mhz:
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Fsys = PLL0 (192Mhz)
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Fbus = Fsys/6
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CPU = Fbus, COP = Fbus */
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CLKCTRL = (1<<31) | (3<<28) | (5<<4);
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}
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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cpu_frequency = frequency;
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}
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#endif
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