From 3b1c3881f05c9a0645a21ca0d9d2bb8d7aea10c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= Date: Sun, 11 Apr 2010 18:26:45 +0000 Subject: [PATCH] as3525v2: only clear DIV0 bits in set_cpu_frequency() (not bit 6) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25595 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/system-as3525.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index b1b1967936..0b1884aa16 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c @@ -439,7 +439,7 @@ void set_cpu_frequency(long frequency) if(frequency == CPUFREQ_MAX) { /* Change PCLK while FCLK is low, so it doesn't go too high */ - CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0 << 2); + CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0 << 2); delay = 40; while(delay--) asm("nop"); @@ -461,7 +461,7 @@ void set_cpu_frequency(long frequency) delay = 40; while(delay--) asm("nop"); /* Change PCLK after FCLK is low, so it doesn't go too high */ - CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2); + CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2); delay = 40; while(delay--) asm("nop"); }