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Hosted targets Fix timer cycle calculation overflow

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at 1 GHZ the intermediate calculation for cycles overflows 32 bits
this makes timer fail even with sensible values
solution divide both sides by 100

Change-Id: I18a4054c2d06fb72531d5496bba562f71b03984f
This commit is contained in:
William Wilgus 2020-10-23 11:29:38 -04:00 • committed by William Wilgus
parent 186dbb4527
commit 3a7a46d1c0
2 changed files with 5 additions and 2 deletions
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2
firmware/target/hosted/kernel-unix.c
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@ -104,7 +104,7 @@ void tick_start(unsigned int interval_in_ms)
}
#define cycles_to_microseconds(cycles) \
((int)((1000000*cycles)/TIMER_FREQ))
((int)((10000*cycles)/(TIMER_FREQ / 100)))
static timer_t timer_tid;