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Bootloader USB mode for PP502x. Enable only on GoGear SA9200 for the time being. Add HAVE_BOOTLOADER_USB_MODE to config if BOOTLOADER is defined to enable it. Clean up some kernel stuff a little to support it. Mess up a bunch of other stuff (hopefully not too badly).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29053 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2011-01-15 08:19:30 +00:00
parent 53db95417d
commit 3a1127785b
26 changed files with 842 additions and 160 deletions
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149
firmware/target/arm/philips/boot.lds
View file

@ -3,11 +3,12 @@
ENTRY(start)
OUTPUT_FORMAT(elf32-littlearm)
OUTPUT_ARCH(arm)
STARTUP(target/arm/crt0-pp-bl.o)
STARTUP(target/arm/crt0-pp502x-bl-usb.o)
#define DRAMSIZE (MEMORYSIZE * 0x100000)
#define DRAMORIG 0x10000000
#define DRAMORIG 0x01000000 /* Load at 16 MB */
#define DRAMSIZE 0x00100000 /* 1MB for bootloader */
#define MEMEND (MEMORYSIZE*0x100000) /* From virtual mapping at 0 */
#define NOCACHE_BASE 0x10000000
#ifndef IRAMORIG
#define IRAMORIG 0x40000000
#endif
@ -15,6 +16,8 @@ STARTUP(target/arm/crt0-pp-bl.o)
#define FLASHORIG 0x001f0000
#define FLASHSIZE 2M
#define CACHEALIGN_SIZE 16
MEMORY
{
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
@ -23,44 +26,112 @@ MEMORY
SECTIONS
{
. = IRAMORIG;
. = DRAMORIG;
_loadaddress = . + NOCACHE_BASE;
.text : {
*(.init.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
} > IRAM
.text :
{
*(.init.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
. = ALIGN(0x4);
} > DRAM
.data : {
*(.icode)
*(.irodata)
*(.idata)
*(.data*)
*(.ncdata*)
*(.rodata*)
_dataend = . ;
} > IRAM
.rodata :
{
*(.rodata) /* problems without this, dunno why */
*(.rodata*)
*(.rodata.str1.1)
*(.rodata.str1.4)
. = ALIGN(0x4);
} > DRAM
.stack (NOLOAD) : {
*(.stack)
_stackbegin = .;
stackbegin = .;
. += 0x2000;
_stackend = .;
stackend = .;
} > IRAM
.data :
{
*(.data*)
. = ALIGN(0x4);
} > DRAM
/* The bss section is too large for IRAM - we just move it 16MB into the
DRAM */
/* .ncdata section is placed at uncached physical alias address and is
* loaded at the proper cached virtual address - no copying is
* performed in the init code */
.ncdata . + NOCACHE_BASE :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncdata*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
. = DRAMORIG;
.bss . + (16*1024*1024) (NOLOAD) : {
_edata = .;
*(.bss*);
*(.ibss);
*(COMMON)
*(.ncbss*);
_end = .;
} > DRAM
/DISCARD/ . - NOCACHE_BASE :
{
*(.eh_frame)
} > DRAM
_noloaddram = .;
.ibss IRAMORIG (NOLOAD) :
{
_iedata = .;
*(.qharray)
*(.ibss)
. = ALIGN(0x4);
_iend = .;
} > IRAM
.iram _iend :
{
_iramstart = .;
*(.icode)
*(.irodata)
*(.idata)
_iramend = .;
} > IRAM AT> DRAM
_iramcopy = LOADADDR(.iram);
.loadaddressend :
{
_loadaddressend = . + NOCACHE_BASE;
} AT> DRAM
.stack (NOLOAD) :
{
. = ALIGN(8);
*(.stack)
stackbegin = .;
. += 0x2000;
stackend = .;
} > IRAM
/* .bss and .ncbss are treated as a single section to use one init loop
* to zero them - note "_edata" and "_end" */
.bss _noloaddram (NOLOAD) :
{
_edata = .;
*(.bss*)
*(COMMON)
} > DRAM
.ncbss . + NOCACHE_BASE (NOLOAD) :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncbss*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
/* This will be aligned by preceding alignments */
.endaddr . - NOCACHE_BASE (NOLOAD) :
{
_end = .;
} > DRAM
/* Reference to all DRAM after loaded bootloader image */
.freebuffer _end (NOLOAD) :
{
. = ALIGN(4);
freebuffer = .;
. = MEMEND-1;
freebufferend = .;
}
}

4
firmware/target/arm/philips/sa9200/button-sa9200.c
View file

@ -119,6 +119,10 @@ void button_int(void)
void button_init_device(void)
{
}
void button_int(void)
{
}
#endif /* BOOTLOADER */
bool button_hold(void)

3
firmware/target/arm/philips/sa9200/button-target.h
View file

@ -34,10 +34,7 @@
bool button_hold(void);
void button_init_device(void);
int button_read_device(void);
#ifndef BOOTLOADER
void button_int(void);
#endif
/* Main unit's buttons */
#define BUTTON_POWER 0x00000001