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Ingenic Jz4740: enable IRAM (only core, without ibss)

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21331 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2009-06-18 18:16:15 +00:00
parent 0181bc42c9
commit 2fb6396f5a
3 changed files with 15 additions and 34 deletions
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5
firmware/export/config.h
View file

@ -639,13 +639,14 @@ Lyre prototype 1*/
(CONFIG_CPU == AS3525 && MEMORYSIZE > 2) || /* AS3525 +2MB: core, plugins, codecs */ \ (CONFIG_CPU == AS3525 && MEMORYSIZE > 2) || /* AS3525 +2MB: core, plugins, codecs */ \
(CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525 2MB:core only */ \ (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525 2MB:core only */ \
(CONFIG_CPU == PNX0101) || \ (CONFIG_CPU == PNX0101) || \
(CONFIG_CPU == S5L8700)) /* Samsung S5L8700: core, plugins, codecs */ (CONFIG_CPU == S5L8700)) /* Samsung S5L8700: core, plugins, codecs */ || \
(CONFIG_CPU == JZ4732 && !defined(PLUGIN) && !defined(CODEC)) /* Jz4740: core only */
#define ICODE_ATTR __attribute__ ((section(".icode"))) #define ICODE_ATTR __attribute__ ((section(".icode")))
#define ICONST_ATTR __attribute__ ((section(".irodata"))) #define ICONST_ATTR __attribute__ ((section(".irodata")))
#define IDATA_ATTR __attribute__ ((section(".idata"))) #define IDATA_ATTR __attribute__ ((section(".idata")))
#define IBSS_ATTR __attribute__ ((section(".ibss"))) #define IBSS_ATTR __attribute__ ((section(".ibss")))
#define USE_IRAM #define USE_IRAM
#if CONFIG_CPU != SH7034 && (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) #if CONFIG_CPU != SH7034 && (CONFIG_CPU != AS3525 || MEMORYSIZE > 2) && CONFIG_CPU != JZ4732
#define PLUGIN_USE_IRAM #define PLUGIN_USE_IRAM
#endif #endif
#if defined(CPU_ARM) #if defined(CPU_ARM)

32
firmware/target/mips/ingenic_jz47xx/app.lds
View file

@ -16,7 +16,7 @@ STARTUP(target/mips/ingenic_jz47xx/crt0.o)
#define DRAMORIG 0x80004000 #define DRAMORIG 0x80004000
#define IRAMORIG 0x80000000 #define IRAMORIG 0x80000000
#define IRAMSIZE (16K-0x220) #define IRAMSIZE 16K
/* End of the audio buffer, where the codec buffer starts */ /* End of the audio buffer, where the codec buffer starts */
#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
@ -41,14 +41,14 @@ SECTIONS
*(.init.text); *(.init.text);
*(.text*); *(.text*);
} > DRAM } > DRAM
. = ALIGN(4); . = ALIGN(4);
.rodata : .rodata :
{ {
*(.rodata*); *(.rodata*);
} > DRAM } > DRAM
. = ALIGN(4); . = ALIGN(4);
.data : .data :
@ -57,9 +57,9 @@ SECTIONS
*(.sdata*); *(.sdata*);
*(.rel.dyn); *(.rel.dyn);
} > DRAM } > DRAM
. = ALIGN(4); . = ALIGN(4);
/* Set the load address of .iram at the same address as .bss /* Set the load address of .iram at the same address as .bss
* so RAM won't be wasted as .iram in the end will get copied * so RAM won't be wasted as .iram in the end will get copied
* to IRAM. */ * to IRAM. */
@ -74,7 +74,7 @@ SECTIONS
. = 0x200; . = 0x200;
*(.vectors.4); *(.vectors.4);
*(.vectors); *(.vectors);
*(.icode); *(.icode);
*(.irodata); *(.irodata);
*(.idata); *(.idata);
@ -83,9 +83,9 @@ SECTIONS
_iramend = .; _iramend = .;
} > IRAM } > IRAM
_iramcopy = LOADADDR(.iram); _iramcopy = LOADADDR(.iram);
. = ALIGN(4); . = ALIGN(4);
.stack (NOLOAD): .stack (NOLOAD):
{ {
*(.stack); *(.stack);
@ -93,28 +93,20 @@ SECTIONS
. += 0x2000; . += 0x2000;
stackend = .; stackend = .;
} > IRAM } > IRAM
. = ALIGN(4);
.bss (NOLOAD): .bss (NOLOAD):
{ {
_edata = .; _edata = .;
*(.sbss*); *(.sbss*);
*(.bss*); *(.bss*);
*(.ibss*); /* Don't put this in IRAM as there's not enough space */
*(COMMON); *(COMMON);
*(.scommon*); *(.scommon*);
_end = .; _end = .;
} > DRAM } > DRAM
. = ALIGN(4); . = ALIGN(4);
.ibss (NOLOAD) :
{
_iedata = .;
*(.ibss*);
_iend = .;
} > IRAM
.audiobuf ALIGN(4) : .audiobuf ALIGN(4) :
{ {
audiobuffer = .; audiobuffer = .;
@ -134,7 +126,7 @@ SECTIONS
{ {
pluginbuf = .; pluginbuf = .;
} }
/DISCARD/ : /DISCARD/ :
{ {
*(.eh_frame); *(.eh_frame);

12
firmware/target/mips/ingenic_jz47xx/crt0.S
View file

@ -147,18 +147,6 @@ _bss_loop:
sw zero, 0(t0) sw zero, 0(t0)
bne t0, t1, _bss_loop bne t0, t1, _bss_loop
addiu t0, 4 addiu t0, 4
/*
----------------------------------------------------
Clear IBSS section
----------------------------------------------------
*/
la t0, _iedata
la t1, _iend
_ibss_loop:
sw zero, 0(t0)
bne t0, t1, _ibss_loop
addiu t0, 4
/* /*
---------------------------------------------------- ----------------------------------------------------