forked from len0rd/rockbox
ARMv6: Optimize interrupt enable/disable with cpsie and cpsid. Section off system-arm.h by ARM_ARCH rather than checking within each implementation.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19905 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
701a593c5d
commit
28dbd584fb
1 changed files with 178 additions and 105 deletions
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@ -21,86 +21,12 @@
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#ifndef SYSTEM_ARM_H
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#define SYSTEM_ARM_H
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/* Common to all ARM_ARCH */
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#define nop \
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asm volatile ("nop")
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void __div0(void);
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/* This gets too complicated otherwise with all the ARM variation and would
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have conflicts with another system-target.h elsewhere so include a
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subheader from here. */
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static inline uint16_t swap16(uint16_t value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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#if ARM_ARCH >= 6
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uint32_t retval;
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asm volatile ("revsh %0, %1" /* xxAB */
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: "=r"(retval) : "r"((uint32_t)value)); /* xxBA */
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return retval;
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#else
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return (value >> 8) | (value << 8);
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#endif
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}
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static inline uint32_t swap32(uint32_t value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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#if ARM_ARCH >= 6
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uint32_t retval;
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asm volatile ("rev %0, %1" /* ABCD */
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: "=r"(retval) : "r"(value)); /* DCBA */
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return retval;
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#else
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uint32_t tmp;
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asm volatile (
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"eor %1, %0, %0, ror #16 \n\t"
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"bic %1, %1, #0xff0000 \n\t"
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"mov %0, %0, ror #8 \n\t"
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"eor %0, %0, %1, lsr #8 \n\t"
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: "+r" (value), "=r" (tmp)
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);
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return value;
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#endif
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}
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static inline uint32_t swap_odd_even32(uint32_t value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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#if ARM_ARCH >= 6
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uint32_t retval;
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asm volatile ("rev16 %0, %1" /* ABCD */
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: "=r"(retval) : "r"(value)); /* BADC */
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return retval;
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#else
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uint32_t tmp;
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asm volatile ( /* ABCD */
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"bic %1, %0, #0x00ff00 \n\t" /* AB.D */
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"bic %0, %0, #0xff0000 \n\t" /* A.CD */
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"mov %0, %0, lsr #8 \n\t" /* .A.C */
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"orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */
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: "+r" (value), "=r" (tmp) /* BADC */
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);
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return value;
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#endif
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}
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/* Core-level interrupt masking */
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/* This one returns the old status */
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#define IRQ_ENABLED 0x00
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#define IRQ_DISABLED 0x80
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#define IRQ_STATUS 0x80
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@ -117,6 +43,27 @@ static inline uint32_t swap_odd_even32(uint32_t value)
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#define set_fiq_status(status) \
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set_interrupt_status((status), FIQ_STATUS)
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#define disable_irq_save() \
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disable_interrupt_save(IRQ_STATUS)
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#define disable_fiq_save() \
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disable_interrupt_save(FIQ_STATUS)
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#define restore_irq(cpsr) \
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restore_interrupt(cpsr)
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#define restore_fiq(cpsr) \
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restore_interrupt(cpsr)
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#define disable_irq() \
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disable_interrupt(IRQ_STATUS)
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#define enable_irq() \
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enable_interrupt(IRQ_STATUS)
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#define disable_fiq() \
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disable_interrupt(FIQ_STATUS)
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#define enable_fiq() \
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enable_interrupt(FIQ_STATUS)
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/* Core-level interrupt masking */
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static inline int set_interrupt_status(int status, int mask)
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{
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unsigned long cpsr;
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@ -133,6 +80,161 @@ static inline int set_interrupt_status(int status, int mask)
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return oldstatus;
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}
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static inline void restore_interrupt(int cpsr)
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{
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/* Set cpsr_c from value returned by disable_interrupt_save
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* or set_interrupt_status */
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asm volatile ("msr cpsr_c, %0" : : "r"(cpsr));
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}
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/* ARM_ARCH version section for architecture*/
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#if ARM_ARCH >= 6
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static inline uint16_t swap16(uint16_t value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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uint32_t retval;
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asm volatile ("revsh %0, %1" /* xxAB */
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: "=r"(retval) : "r"((uint32_t)value)); /* xxBA */
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return retval;
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}
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static inline uint32_t swap32(uint32_t value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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uint32_t retval;
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asm volatile ("rev %0, %1" /* ABCD */
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: "=r"(retval) : "r"(value)); /* DCBA */
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return retval;
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}
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static inline uint32_t swap_odd_even32(uint32_t value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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uint32_t retval;
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asm volatile ("rev16 %0, %1" /* ABCD */
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: "=r"(retval) : "r"(value)); /* BADC */
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return retval;
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}
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static inline void enable_interrupt(int mask)
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{
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/* Clear I and/or F disable bit */
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/* mask is expected to be constant and so only relevent branch
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* is preserved */
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switch (mask & IRQ_FIQ_STATUS)
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{
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case IRQ_STATUS:
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asm volatile ("cpsie i");
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break;
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case FIQ_STATUS:
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asm volatile ("cpsie f");
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break;
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case IRQ_FIQ_STATUS:
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asm volatile ("cpsie if");
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break;
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}
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}
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static inline void disable_interrupt(int mask)
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{
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/* Set I and/or F disable bit */
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/* mask is expected to be constant and so only relevent branch
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* is preserved */
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switch (mask & IRQ_FIQ_STATUS)
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{
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case IRQ_STATUS:
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asm volatile ("cpsid i");
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break;
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case FIQ_STATUS:
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asm volatile ("cpsid f");
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break;
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case IRQ_FIQ_STATUS:
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asm volatile ("cpsid if");
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break;
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}
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}
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static inline int disable_interrupt_save(int mask)
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{
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/* Set I and/or F disable bit and return old cpsr value */
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int cpsr;
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/* mask is expected to be constant and so only relevent branch
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* is preserved */
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asm volatile("mrs %0, cpsr" : "=r"(cpsr));
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switch (mask & IRQ_FIQ_STATUS)
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{
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case IRQ_STATUS:
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asm volatile ("cpsid i");
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break;
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case FIQ_STATUS:
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asm volatile ("cpsid f");
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break;
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case IRQ_FIQ_STATUS:
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asm volatile ("cpsid if");
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break;
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}
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return cpsr;
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}
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#else /* ARM_ARCH < 6 */
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static inline uint16_t swap16(uint16_t value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline uint32_t swap32(uint32_t value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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uint32_t tmp;
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asm volatile (
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"eor %1, %0, %0, ror #16 \n\t"
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"bic %1, %1, #0xff0000 \n\t"
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"mov %0, %0, ror #8 \n\t"
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"eor %0, %0, %1, lsr #8 \n\t"
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: "+r" (value), "=r" (tmp)
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);
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return value;
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}
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static inline uint32_t swap_odd_even32(uint32_t value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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uint32_t tmp;
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asm volatile ( /* ABCD */
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"bic %1, %0, #0x00ff00 \n\t" /* AB.D */
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"bic %0, %0, #0xff0000 \n\t" /* A.CD */
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"mov %0, %0, lsr #8 \n\t" /* .A.C */
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"orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */
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: "+r" (value), "=r" (tmp) /* BADC */
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);
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return value;
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}
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static inline void enable_interrupt(int mask)
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{
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/* Clear I and/or F disable bit */
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@ -155,18 +257,6 @@ static inline void disable_interrupt(int mask)
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: "=&r"(tmp) : "i"(mask));
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}
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#define disable_irq() \
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disable_interrupt(IRQ_STATUS)
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#define enable_irq() \
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enable_interrupt(IRQ_STATUS)
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#define disable_fiq() \
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disable_interrupt(FIQ_STATUS)
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#define enable_fiq() \
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enable_interrupt(FIQ_STATUS)
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static inline int disable_interrupt_save(int mask)
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{
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/* Set I and/or F disable bit and return old cpsr value */
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@ -180,23 +270,6 @@ static inline int disable_interrupt_save(int mask)
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return cpsr;
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}
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#define disable_irq_save() \
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disable_interrupt_save(IRQ_STATUS)
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#define disable_fiq_save() \
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disable_interrupt_save(FIQ_STATUS)
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static inline void restore_interrupt(int cpsr)
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{
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/* Set cpsr_c from value returned by disable_interrupt_save
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* or set_interrupt_status */
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asm volatile ("msr cpsr_c, %0" : : "r"(cpsr));
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}
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#define restore_irq(cpsr) \
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restore_interrupt(cpsr)
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#define restore_fiq(cpsr) \
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restore_interrupt(cpsr)
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#endif /* ARM_ARCH */
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#endif /* SYSTEM_ARM_H */
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