forked from len0rd/rockbox
FS#11765: Improve AMSv1 Battery Life by Lowering CPU and Peripheral clocks. Unboosted CPU and peripheral clock is now 31MHz. Boosted CPU and pclk are 186MHz and 62MHz, respectively.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28834 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Fred Bauer
parent
990cbf302e
commit
279dff1c21
4 changed files with 94 additions and 16 deletions
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@ -114,17 +114,19 @@
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/* *5/8 = 240MHz 120, 80, 60, 48, 40 */
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//#define AS3525_PLLA_SETTING 0x2630
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#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
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#define AS3525_FCLK_PREDIV 2 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
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/* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */
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#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */
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#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */
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#define AS3525_FCLK_FREQ 186000000 /* Boosted FCLK frequency - over 200MHz */
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/* requires CVDDp bumped to 1.2V */
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#define AS3525_DRAM_FREQ 31000000 /* Initial DRAM frequency */
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#define AS3525_DRAM_FREQ_BOOSTED 62000000
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/* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
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#endif /* CONFIG_CPU == AS3525v2 */
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#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */
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#define AS3525_PCLK_FREQ_BOOSTED (AS3525_DRAM_FREQ_BOOSTED/1)
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#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */
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/** ****************************************************************************/
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@ -169,6 +171,9 @@
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/*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/
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#define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/
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#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
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#define AS3525_PCLK_DIV1_BOOSTED (CLK_DIV(AS3525_DRAM_FREQ_BOOSTED, AS3525_PCLK_FREQ_BOOSTED) - 1)
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#define AS3525_PCLK_DIV0_BOOSTED (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ_BOOSTED) - 1)
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#else
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#define AS3525_PCLK_SEL AS3525_CLK_FCLK
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@ -179,8 +184,10 @@
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/* PCLK as Source */
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#define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
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#define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
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#define AS3525_I2C_PRESCALER_BOOSTED CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_I2C_FREQ)
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#define AS3525_I2C_FREQ 400000
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#define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
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#define AS3525_SD_IDENT_DIV_BOOSTED ((CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_SD_IDENT_FREQ) / 2) - 1)
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#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
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#define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */
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#define AS3525_SSP_FREQ 12000000
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@ -182,7 +182,12 @@ static int calc_freq(int clk)
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return 0;
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}
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case CLK_I2C:
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return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER;
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#if CONFIG_CPU == AS3525
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if (cpu_frequency == CPUFREQ_MAX)
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return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER_BOOSTED;
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else
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#endif
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return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER;
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case CLK_I2SI:
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switch((CGU_AUDIO>>12) & 3) {
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case 0:
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@ -218,7 +223,7 @@ static int calc_freq(int clk)
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case CLK_SD_MCLK_MSD:
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if(!(MCI_SD & (1<<8)))
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return 0;
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else if(MCI_SD & (1<<10))
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else if(MCI_SD & (1<<10)) /* bypass */
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return calc_freq(CLK_PCLK);
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else
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return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2);
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@ -347,7 +352,7 @@ bool __dbg_hw_info(void)
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calc_freq(CLK_SD_MCLK_NAND)/1000000);
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#ifdef HAVE_MULTIDRIVE
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lcd_putsf(0, line++, "uSD :%3dMHz %3dMHz",
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((AS3525_PCLK_FREQ/ 1000000) /
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((calc_freq(CLK_PCLK)/ 1000000) /
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((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))),
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calc_freq(CLK_SD_MCLK_MSD)/1000000);
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#endif
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@ -116,9 +116,8 @@ static void init_pl180_controller(const int drive);
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static tCardInfo card_info[NUM_DRIVES];
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/* maximum timeouts recommanded in the SD Specification v2.00 */
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#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
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#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
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#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 100) /* 100 ms */
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#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 250) /* 250 ms */
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/* for compatibility */
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static long last_disk_activity = -1;
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@ -140,6 +139,8 @@ static struct wakeup transfer_completion_signal;
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static volatile unsigned int transfer_error[NUM_VOLUMES];
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#define PL180_MAX_TRANSFER_ERRORS 10
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extern long cpu_frequency;
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#define UNALIGNED_NUM_SECTORS 10
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static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */
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static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
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@ -283,7 +284,7 @@ static bool send_cmd(const int drive, const int cmd, const int arg,
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#define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */
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#define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */
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#define MCI_IDENTSPEED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV) /* IDENT */
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#define MCI_IDENTSPEED_BOOSTED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV_BOOSTED)
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static int sd_init_card(const int drive)
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{
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unsigned long response;
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@ -293,7 +294,10 @@ static int sd_init_card(const int drive)
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card_info[drive].rca = 0;
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/* MCLCK on and set to 400kHz ident frequency */
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MCI_CLOCK(drive) = MCI_IDENTSPEED;
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if (cpu_frequency == CPUFREQ_MAX)
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MCI_CLOCK(drive) = MCI_IDENTSPEED_BOOSTED;
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else
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MCI_CLOCK(drive) = MCI_IDENTSPEED;
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/* 100 - 400kHz clock required for Identification Mode */
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/* Start of Card Identification Mode ************************************/
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@ -375,8 +379,12 @@ static int sd_init_card(const int drive)
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MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */
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#if defined(HAVE_MULTIDRIVE)
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else
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/* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
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MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
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{ /* PCLK = 31Mhz (62 boosted) MCI = 31Mhz(hs) or 15.5 */
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if (cpu_frequency == CPUFREQ_MAX )
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MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
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else
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MCI_CLOCK(drive) = (hs_card ? MCI_FULLSPEED : MCI_HALFSPEED);
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}
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#endif
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/* CMD7 w/rca: Select card to put it in TRAN state */
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@ -523,6 +531,26 @@ static void sd_thread(void)
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}
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}
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#ifdef HAVE_MULTIDRIVE
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void sd_set_boosted_divider(void)
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{
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if ( !sd_enabled )
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return;
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/* 62Mhz/2 - 62/4 */
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MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ?
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MCI_HALFSPEED : MCI_QUARTERSPEED);
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}
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void sd_set_unboosted_divider(void)
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{
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if ( !sd_enabled )
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return;
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/* 31Mhz/1 - 31/2 */
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MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ?
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MCI_FULLSPEED : MCI_HALFSPEED);
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}
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#endif
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static void init_pl180_controller(const int drive)
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{
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MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
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@ -33,6 +33,12 @@
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#include "backlight-target.h"
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#include "lcd.h"
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/* FIXME */
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#define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C))
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#define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20))
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extern void sd_set_boosted_divider(void);
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extern void sd_set_unboosted_divider(void);
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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@ -286,7 +292,12 @@ void system_init(void)
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#endif
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/* Initialize power management settings */
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#if CONFIG_CPU == AS3525
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ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING|CVDD_1_10);
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#else
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ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
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#endif
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#if CONFIG_TUNER
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fmradio_i2c_init();
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#endif
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@ -354,7 +365,9 @@ void set_cpu_frequency(long frequency)
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{
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if(frequency == CPUFREQ_MAX)
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{
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#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
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#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000)
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/* This doesn't work anymore. It was written before ascodec
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was switched to use interrupts */
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/* Increasing frequency so boost voltage before change */
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ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
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@ -374,10 +387,35 @@ void set_cpu_frequency(long frequency)
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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#ifdef HAVE_MULTIDRIVE
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/* Set uSD frequency */
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sd_set_boosted_divider();
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#endif
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/* Set I2C frequency */
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I2C2_CPSR0 = AS3525_I2C_PRESCALER_BOOSTED & 0xFF; /* 8 lsb */
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I2C2_CPSR1 = (AS3525_I2C_PRESCALER_BOOSTED >> 8) & 0x3; /* 2 msb */
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/* Set PCLK frequency */
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CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */
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(AS3525_PCLK_DIV0_BOOSTED << 2) |
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(AS3525_PCLK_DIV1_BOOSTED << 6) |
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AS3525_PCLK_SEL);
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cpu_frequency = CPUFREQ_MAX;
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}
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else
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{
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/* Set I2C frequency */
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I2C2_CPSR0 = AS3525_I2C_PRESCALER & 0xFF; /* 8 lsb */
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I2C2_CPSR1 = (AS3525_I2C_PRESCALER >> 8) & 0x3; /* 2 msb */
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/* Set PCLK frequency */
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CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */
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(AS3525_PCLK_DIV0 << 2) |
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(AS3525_PCLK_DIV1 << 6) |
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AS3525_PCLK_SEL);
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#ifdef HAVE_MULTIDRIVE
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/* Set uSD frequency */
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sd_set_unboosted_divider();
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#endif
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asm volatile(
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"mrc p15, 0, r0, c1, c0 \n"
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"bic r0, r0, #3<<30 \n" /* fastbus clocking */
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@ -387,7 +425,7 @@ void set_cpu_frequency(long frequency)
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/* FCLK is unused so put it to the lowest freq we can */
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CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN);
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#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
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#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000)
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/* Decreasing frequency so reduce voltage after change */
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ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
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#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
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