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Gigabeat S mixer: Make some progress. Get the tick and core sleep working using the AVIC. Redo the startup code to remap from IRAM and not include the lcd driver frambuffer in the remapping (until it can be moved). Clean up LCD driver. For other misc. changes, see the diffs. Now it progresses to ATA init and fails with -11 but without crashing or hanging. Replace all bootloaders.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16216 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-02-05 04:43:19 +00:00
parent 3f85a4bc97
commit 1f021af60c
17 changed files with 898 additions and 1216 deletions
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566
firmware/export/imx31l.h
View file

@ -19,16 +19,21 @@
/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
#define REG8_PTR_T volatile unsigned char *
#define REG16_PTR_T volatile unsigned short *
#define REG32_PTR_T volatile unsigned long *
#define TTB_BASE_ADDR (0x80000000 + (64*1024*1024)-TTB_SIZE)
#define IRAM_BASE_ADDR 0x1fffc000
#define L2CC_BASE_ADDR 0x30000000
/*Frame Buffer and TTB defines from gigabeat f/x build*/
#define LCDSADDR1 (*(volatile int *)0x80100000) /* STN/TFT: frame buffer start address 1 */
#define FRAME1 ((short *)0x80100000) //Foreground FB
#define FRAME2 ((short *)0x84100000) //Background FB - Set to Graphic Window, hence the reason why text is only visible
//when background memory is written.
#define FRAME ((short *)0x80100000) /* Framebuffer */
#define LCD_BUFFER_SIZE ((320*240*2))
#define TTB_SIZE (0x4000)
#define TTB_BASE ((unsigned int *)(0x88000000 + (64*1024*1024)-TTB_SIZE))
#define TTB_BASE ((unsigned int *)TTB_BASE_ADDR)
#define FRAME1 ALIGN_DOWN((TTB_BASE - LCD_BUFFER_SIZE), 32)
#define FRAME2 ALIGN_DOWN((TTB_BASE - LCD_BUFFER_SIZE), 32)
/*
* AIPS 1
*/
@ -97,136 +102,126 @@
#define PWM_BASE_ADDR 0x53FE0000
#define RTIC_BASE_ADDR 0x53FEC000
#define WDOG1_BASE_ADDR WDOG_BASE_ADDR
#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
#define WDOG1_BASE_ADDR WDOG_BASE_ADDR
#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
/* IPU */
#define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
#define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
#define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
#define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
#define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
#define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
#define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
#define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
#define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
#define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
#define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
#define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
#define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
#define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
#define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
#define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
#define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
#define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
#define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
#define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
#define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
/* ATA */
#define TIME_OFF (*(volatile unsigned char*)0x43F8C000)
#define TIME_ON (*(volatile unsigned char*)0x43F8C001)
#define TIME_1 (*(volatile unsigned char*)0x43F8C002)
#define TIME_2W (*(volatile unsigned char*)0x43F8C003)
#define TIME_2R (*(volatile unsigned char*)0x43F8C004)
#define TIME_AX (*(volatile unsigned char*)0x43F8C005)
#define TIME_PIO_RDX (*(volatile unsigned char*)0x43F8C00F)
#define TIME_4 (*(volatile unsigned char*)0x43F8C007)
#define TIME_9 (*(volatile unsigned char*)0x43F8C008)
#define TIME_OFF (*(REG8_PTR_T)0x43F8C000)
#define TIME_ON (*(REG8_PTR_T)0x43F8C001)
#define TIME_1 (*(REG8_PTR_T)0x43F8C002)
#define TIME_2W (*(REG8_PTR_T)0x43F8C003)
#define TIME_2R (*(REG8_PTR_T)0x43F8C004)
#define TIME_AX (*(REG8_PTR_T)0x43F8C005)
#define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F)
#define TIME_4 (*(REG8_PTR_T)0x43F8C007)
#define TIME_9 (*(REG8_PTR_T)0x43F8C008)
/* Timers */
#define EPITCR1 (*(volatile long*)EPIT1_BASE_ADDR)
#define EPITSR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x04))
#define EPITLR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x08))
#define EPITCMPR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x0C))
#define EPITCNT1 (*(volatile long*)(EPIT1_BASE_ADDR+0x10))
#define EPITCR2 (*(volatile long*)EPIT2_BASE_ADDR)
#define EPITSR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x04))
#define EPITLR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x08))
#define EPITCMPR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x0C))
#define EPITCNT2 (*(volatile long*)(EPIT2_BASE_ADDR+0x10))
#define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
#define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
#define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
#define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
#define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
#define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
#define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
#define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
#define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
#define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
/* GPIO */
#define GPIO1_DR (*(volatile long*)GPIO1_BASE_ADDR)
#define GPIO1_GDIR (*(volatile long*)(GPIO1_BASE_ADDR+0x04))
#define GPIO1_PSR (*(volatile long*)(GPIO1_BASE_ADDR+0x08))
#define GPIO1_ICR1 (*(volatile long*)(GPIO1_BASE_ADDR+0x0C))
#define GPIO1_ICR2 (*(volatile long*)(GPIO1_BASE_ADDR+0x10))
#define GPIO1_IMR (*(volatile long*)(GPIO1_BASE_ADDR+0x14))
#define GPIO1_ISR (*(volatile long*)(GPIO1_BASE_ADDR+0x18))
#define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
#define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
#define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
#define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
#define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
#define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
#define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
#define GPIO2_DR (*(volatile long*)GPIO2_BASE_ADDR)
#define GPIO2_GDIR (*(volatile long*)(GPIO2_BASE_ADDR+0x04))
#define GPIO2_PSR (*(volatile long*)(GPIO2_BASE_ADDR+0x08))
#define GPIO2_ICR1 (*(volatile long*)(GPIO2_BASE_ADDR+0x0C))
#define GPIO2_ICR2 (*(volatile long*)(GPIO2_BASE_ADDR+0x10))
#define GPIO2_IMR (*(volatile long*)(GPIO2_BASE_ADDR+0x14))
#define GPIO2_ISR (*(volatile long*)(GPIO2_BASE_ADDR+0x18))
#define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
#define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
#define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
#define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
#define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
#define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
#define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
#define GPIO3_DR (*(volatile long*)GPIO3_BASE_ADDR)
#define GPIO3_GDIR (*(volatile long*)(GPIO3_BASE_ADDR+0x04))
#define GPIO3_PSR (*(volatile long*)(GPIO3_BASE_ADDR+0x08))
#define GPIO3_ICR1 (*(volatile long*)(GPIO3_BASE_ADDR+0x0C))
#define GPIO3_ICR2 (*(volatile long*)(GPIO3_BASE_ADDR+0x10))
#define GPIO3_IMR (*(volatile long*)(GPIO3_BASE_ADDR+0x14))
#define GPIO3_ISR (*(volatile long*)(GPIO3_BASE_ADDR+0x18))
#define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
#define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
#define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
#define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
#define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
#define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
#define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
/* SPI */
#define CSPI_RXDATA1 (*(volatile long*)CSPI1_BASE_ADDR)
#define CSPI_TXDATA1 (*(volatile long*)(CSPI1_BASE_ADDR+0x04))
#define CSPI_CONREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x08))
#define CSPI_INTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x0C))
#define CSPI_DMAREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x10))
#define CSPI_STATREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x14))
#define CSPI_PERIODREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x18))
#define CSPI_TESTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x1C0))
#define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
#define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
#define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
#define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
#define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
#define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
#define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
#define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
#define CSPI_RXDATA2 (*(volatile long*)CSPI2_BASE_ADDR)
#define CSPI_TXDATA2 (*(volatile long*)(CSPI2_BASE_ADDR+0x04))
#define CSPI_CONREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x08))
#define CSPI_INTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x0C))
#define CSPI_DMAREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x10))
#define CSPI_STATREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x14))
#define CSPI_PERIODREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x18))
#define CSPI_TESTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x1C0))
#define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
#define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
#define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
#define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
#define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
#define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
#define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
#define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
/* RTC */
#define RTC_HOURMIN (*(volatile long*)RTC_BASE_ADDR)
#define RTC_SECONDS (*(volatile long*)(RTC_BASE_ADDR+0x04))
#define RTC_ALRM_HM (*(volatile long*)(RTC_BASE_ADDR+0x08))
#define RTC_ALRM_SEC (*(volatile long*)(RTC_BASE_ADDR+0x0C))
#define RTC_CTL (*(volatile long*)(RTC_BASE_ADDR+0x10))
#define RTC_ISR (*(volatile long*)(RTC_BASE_ADDR+0x14))
#define RTC_IENR (*(volatile long*)(RTC_BASE_ADDR+0x18))
#define RTC_STPWCH (*(volatile long*)(RTC_BASE_ADDR+0x1C))
#define RTC_DAYR (*(volatile long*)(RTC_BASE_ADDR+0x20))
#define RTC_DAYALARM (*(volatile long*)(RTC_BASE_ADDR+0x24))
#define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
#define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
#define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
#define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
#define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
#define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
#define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
#define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
#define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
#define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
/* Keypad */
#define KPP_KPCR (*(volatile short*)KPP_BASE_ADDR)
#define KPP_KPSR (*(volatile short*)(KPP_BASE_ADDR+0x2))
#define KPP_KDDR (*(volatile short*)(KPP_BASE_ADDR+0x4))
#define KPP_KPDR (*(volatile short*)(KPP_BASE_ADDR+0x6))
#define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
#define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
#define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
#define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
/* ROMPATCH and AVIC */
#define ROMPATCH_BASE_ADDR 0x60000000
#define AVIC_BASE_ADDR 0x68000000
#define INTCNTL (*(volatile long*)AVIC_BASE_ADDR)
#define NIMASK (*(volatile long*)(AVIC_BASE_ADDR+0x004))
#define INTENNUM (*(volatile long*)(AVIC_BASE_ADDR+0x008))
#define INTDISNUM (*(volatile long*)(AVIC_BASE_ADDR+0x00C))
#define INTENABLEH (*(volatile long*)(AVIC_BASE_ADDR+0x010))
#define INTENABLEL (*(volatile long*)(AVIC_BASE_ADDR+0x014))
#define INTTYPEH (*(volatile long*)(AVIC_BASE_ADDR+0x018))
#define INTTYPEL (*(volatile long*)(AVIC_BASE_ADDR+0x01C))
#define NIPRIORITY7 (*(volatile long*)(AVIC_BASE_ADDR+0x020))
#define NIPRIORITY6 (*(volatile long*)(AVIC_BASE_ADDR+0x024))
#define NIPRIORITY5 (*(volatile long*)(AVIC_BASE_ADDR+0x028))
#define NIPRIORITY4 (*(volatile long*)(AVIC_BASE_ADDR+0x02C))
#define NIPRIORITY3 (*(volatile long*)(AVIC_BASE_ADDR+0x030))
#define NIPRIORITY2 (*(volatile long*)(AVIC_BASE_ADDR+0x034))
#define NIPRIORITY1 (*(volatile long*)(AVIC_BASE_ADDR+0x038))
#define NIPRIORITY0 (*(volatile long*)(AVIC_BASE_ADDR+0x03C))
#define NIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x040))
#define FIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x044))
#define INTSRCH (*(volatile long*)(AVIC_BASE_ADDR+0x048))
#define INTSRCL (*(volatile long*)(AVIC_BASE_ADDR+0x04C))
#define INTFRCH (*(volatile long*)(AVIC_BASE_ADDR+0x050))
#define INTFRCL (*(volatile long*)(AVIC_BASE_ADDR+0x054))
#define NIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x058))
#define NIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x05C))
#define FIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x060))
#define FIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x064))
/* The vectors go all the way up to 63. 4 bytes for each */
#define VECTOR_BASE_ADDR AVIC_BASE_ADDR+0x100
#define VECTOR0 (*(volatile long*)VECTOR_BASE_ADDR)
#define NIDIS (1 << 22)
#define FIDIS (1 << 21)
/* Since AVIC vector registers are NOT used, we reserve some for various
* purposes. Copied from Linux source code. */
#define AVIC_VEC_0 0x100 /* For WFI workaround used by Linux kernel */
#define AVIC_VEC_1 0x104 /* For system revision used by Linux kernel */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_2_0 0x20
#define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
@ -239,11 +234,11 @@
#define NFC_BASE EXT_MEM_CTRL_BASE
#define ESDCTL_BASE 0xB8001000
#define WEIM_BASE_ADDR 0xB8002000
#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
#define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
#define M3IF_BASE 0xB8003000
#define PCMCIA_CTL_BASE 0xB8004000
@ -264,15 +259,52 @@
#define INTERNAL_ROM_VA 0xF0000000
// SDRAM
/*
* SDRAM
*/
#define RAM_BANK0_BASE SDRAM_BASE_ADDR
/*
* IRQ Controller Register Definitions.
*/
#define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04))
#define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18))
#define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
#define AVIC_BASE_ADDR 0x68000000
#define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
#define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
#define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
#define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
#define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
#define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
#define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
#define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
#define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
#define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
#define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
#define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
#define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
#define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
#define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
#define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
#define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
#define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
#define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
#define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
#define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
#define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
#define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
#define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
#define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
#define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
#define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
#define VECTOR(n) (*(REG32_PTR_T)(VECTOR_BASE_ADDR+((n)*4)))
/* The vectors go all the way up to 63. 4 bytes for each */
#define INTCNTL_ABFLAG (1 << 25)
#define INTCNTL_ABFEN (1 << 24)
#define INTCNTL_NIDIS (1 << 22)
#define INTCNTL_FIDIS (1 << 21)
#define INTCNTL_NIAD (1 << 20)
#define INTCNTL_FIAD (1 << 19)
#define INTCNTL_NM (1 << 18)
/* L210 */
#define L2CC_BASE_ADDR 0x30000000
@ -285,17 +317,23 @@
#define L2_CACHE_CLEAN_LINE_REG 0x7B0
#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
#define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
/* CCM */
#define CLKCTL_CCMR (*(volatile long*)(CCM_BASE_ADDR+0x00))
#define CLKCTL_PDR0 (*(volatile long*)(CCM_BASE_ADDR+0x04))
#define CLKCTL_PDR1 (*(volatile long*)(CCM_BASE_ADDR+0x08))
#define CLKCTL_PDR2 (*(volatile long*)(CCM_BASE_ADDR+0x64))
#define CLKCTL_RCSR (*(volatile long*)(CCM_BASE_ADDR+0x0C))
#define CLKCTL_MPCTL (*(volatile long*)(CCM_BASE_ADDR+0x10))
#define CLKCTL_UPCTL (*(volatile long*)(CCM_BASE_ADDR+0x14))
#define CLKCTL_SPCTL (*(volatile long*)(CCM_BASE_ADDR+0x18))
#define CLKCTL_COSR (*(volatile long*)(CCM_BASE_ADDR+0x1C))
#define CLKCTL_PMCR0 (*(volatile long*)(CCM_BASE_ADDR+0x5C))
#define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
#define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
#define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
#define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
#define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
#define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
#define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
#define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
#define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
#define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
#define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
#define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
#define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
#define PLL_REF_CLK 26000000
/* WEIM - CS0 */
@ -311,114 +349,114 @@
#define ESDCTL_ESDMISC 0x10
/* More UART 1 Register defines */
#define URXD1 (*(volatile int*)UART1_BASE_ADDR)
#define UTXD1 (*(volatile int*)(UART1_BASE_ADDR+0x40))
#define UCR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x80))
#define UCR2_1 (*(volatile int* )(UART1_BASE_ADDR+0x84))
#define UCR3_1 (*(volatile int* )(UART1_BASE_ADDR+0x88))
#define UCR4_1 (*(volatile int* )(UART1_BASE_ADDR+0x8C))
#define UFCR1 (*(volatile int *)(UART1_BASE_ADDR+ 0x90))
#define USR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x94))
#define USR2_1 (*(volatile int *)(UART1_BASE_ADDR+0x98))
#define UTS1 (*(volatile int *)(UART1_BASE_ADDR+0xB4))
#define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
#define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
#define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
#define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
#define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
#define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
#define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
#define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
#define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
#define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
/*
* UART Control Register 0 Bit Fields.
*/
#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt
#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
#define EUartUCR1_SNDBRK (1 << 4) // Send break
#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
#define EUartUCR1_DOZE (1 << 1) // Doze
#define EUartUCR1_UARTEN (1 << 0) // UART enabled
#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
#define EUartUCR2_CTSC (1 << 13) // CTS pin control
#define EUartUCR2_CTS (1 << 12) // Clear to send
#define EUartUCR2_ESCEN (1 << 11) // Escape enable
#define EUartUCR2_PREN (1 << 8) // Parity enable
#define EUartUCR2_PROE (1 << 7) // Parity odd/even
#define EUartUCR2_STPB (1 << 6) // Stop
#define EUartUCR2_WS (1 << 5) // Word size
#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
#define EUartUCR2_SRST_ (1 << 0) // SW reset
#define EUartUCR3_PARERREN (1 << 12) // Parity enable
#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
#define EUartUCR4_IRSC (1 << 5) // IR special case
#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
#define EUartUSR1_RTSS (1 << 14) // RTS pin status
#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
#define EUartUSR1_RTSD (1 << 12) // RTS delta
#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
#define EUartUSR2_IDLE (1 << 12) // Idle condition
#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
#define EUartUSR2_WAKE (1 << 7) // Wake
#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
#define EUartUSR2_BRCD (1 << 2) // Break condition
#define EUartUSR2_ORE (1 << 1) // Overrun error
#define EUartUSR2_RDR (1 << 0) // Recv data ready
#define EUartUTS_FRCPERR (1 << 13) // Force parity error
#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
#define EUartUTS_SOFTRST (1 << 0) // Software reset
#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt
#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
#define EUartUCR1_SNDBRK (1 << 4) // Send break
#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
#define EUartUCR1_DOZE (1 << 1) // Doze
#define EUartUCR1_UARTEN (1 << 0) // UART enabled
#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
#define EUartUCR2_CTSC (1 << 13) // CTS pin control
#define EUartUCR2_CTS (1 << 12) // Clear to send
#define EUartUCR2_ESCEN (1 << 11) // Escape enable
#define EUartUCR2_PREN (1 << 8) // Parity enable
#define EUartUCR2_PROE (1 << 7) // Parity odd/even
#define EUartUCR2_STPB (1 << 6) // Stop
#define EUartUCR2_WS (1 << 5) // Word size
#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
#define EUartUCR2_SRST_ (1 << 0) // SW reset
#define EUartUCR3_PARERREN (1 << 12) // Parity enable
#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
#define EUartUCR4_IRSC (1 << 5) // IR special case
#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
#define EUartUSR1_RTSS (1 << 14) // RTS pin status
#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
#define EUartUSR1_RTSD (1 << 12) // RTS delta
#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
#define EUartUSR2_IDLE (1 << 12) // Idle condition
#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
#define EUartUSR2_WAKE (1 << 7) // Wake
#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
#define EUartUSR2_BRCD (1 << 2) // Break condition
#define EUartUSR2_ORE (1 << 1) // Overrun error
#define EUartUSR2_RDR (1 << 0) // Recv data ready
#define EUartUTS_FRCPERR (1 << 13) // Force parity error
#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
#define EUartUTS_SOFTRST (1 << 0) // Software reset
#define DelayTimerPresVal 3
#define DelayTimerPresVal 3
#define L2CC_ENABLED
#define L2CC_ENABLED
/* Assuming 26MHz input clock */
/* PD MFD MFI MFN */
#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
/* UPCTL PD MFD MFI MFN */
#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
@ -434,43 +472,43 @@
#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
#define PBC_BSTAT2 0x2
#define PBC_BCTRL1 0x4
#define PBC_BCTRL1_CLR 0x6
#define PBC_BCTRL2 0x8
#define PBC_BCTRL2_CLR 0xA
#define PBC_BCTRL3 0xC
#define PBC_BCTRL3_CLR 0xE
#define PBC_BCTRL4 0x10
#define PBC_BCTRL4_CLR 0x12
#define PBC_BSTAT1 0x14
#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
#define PBC_BSTAT2 0x2
#define PBC_BCTRL1 0x4
#define PBC_BCTRL1_CLR 0x6
#define PBC_BCTRL2 0x8
#define PBC_BCTRL2_CLR 0xA
#define PBC_BCTRL3 0xC
#define PBC_BCTRL3_CLR 0xE
#define PBC_BCTRL4 0x10
#define PBC_BCTRL4_CLR 0x12
#define PBC_BSTAT1 0x14
#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
#define REDBOOT_IMAGE_SIZE 0x40000
#define REDBOOT_IMAGE_SIZE 0x40000
#define SDRAM_WORKAROUND_FULL_PAGE
#define SDRAM_WORKAROUND_FULL_PAGE
#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
#define ARMHIPG_399_66_66
#define ARMHIPG_399_133_66
#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
#define ARMHIPG_399_66_66
#define ARMHIPG_399_133_66
/* MX31 EVB SDRAM is from 0x80000000, 64M */
#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
#define SDRAM_SIZE 0x04000000
#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
#define SDRAM_SIZE 0x04000000
#define UART_WIDTH_32 /* internal UART is 32bit access only */
#define EXT_UART_x16
#define UART_WIDTH_32 /* internal UART is 32bit access only */
#define EXT_UART_x16
#define UART_WIDTH_32 /* internal UART is 32bit access only */
#define UART_WIDTH_32 /* internal UART is 32bit access only */
#define FLASH_BURST_MODE_ENABLE 1
#define SDRAM_COMPARE_CONST1 0x55555555
#define SDRAM_COMPARE_CONST2 0xAAAAAAAA
#define UART_FIFO_CTRL 0x881
#define TIMEOUT 1000
#define writel(v,a) (*(volatile int *) (a) = (v))
#define readl(a) (*(volatile int *)(a))
#define writew(v,a) (*(volatile short *) (a) = (v))
#define readw(a) (*(volatile short *)(a))
#define FLASH_BURST_MODE_ENABLE 1
#define SDRAM_COMPARE_CONST1 0x55555555
#define SDRAM_COMPARE_CONST2 0xAAAAAAAA
#define UART_FIFO_CTRL 0x881
#define TIMEOUT 1000
#define writel(v,a) (*(REG32_PTR_T)(a) = (v))
#define readl(a) (*(REG32_PTR_T)(a))
#define writew(v,a) (*(REG16_PTR_T)(a) = (v))
#define readw(a) (*(REG16_PTR_T)(a))