Onda VX747:

clean up's, bug fixes and reworks


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19007 a1c6a512-1295-4272-9138-f99709370657

firmware/export/config-ondavx747.h

@@ -33,8 +33,15 @@
 /* For Rolo and boot loader */
 #define MODEL_NUMBER 35
 
-/* define this if you use an ATA controller */
+#define HAVE_ATA_SD
-//#define CONFIG_STORAGE STORAGE_ATA
+#define HAVE_HOTSWAP
+
+//#define CONFIG_STORAGE (STORAGE_NAND | STORAGE_SD)
+#define CONFIG_STORAGE STORAGE_NAND /* Multivolume currently handled at firmware/target/ level */
+
+#define CONFIG_NAND NAND_CC
+
+#define HAVE_MULTIVOLUME
 
 /* define this if you have a bitmap LCD display */
 #define HAVE_LCD_BITMAP

firmware/export/config-ondavx767.h

@@ -36,6 +36,11 @@
 /* define this if you use an ATA controller */
 //#define CONFIG_STORAGE STORAGE_ATA
 
+#define HAVE_ATA_SD
+#define HAVE_HOTSWAP
+
+#define HAVE_MULTIVOLUME
+
 /* define this if you have a bitmap LCD display */
 #define HAVE_LCD_BITMAP
 

firmware/export/config.h

@@ -193,6 +193,7 @@
 #define NAND_IFP7XX  1
 #define NAND_TCC     2
 #define NAND_SAMSUNG 3
+#define NAND_CC      4 /* ChinaChip */
 
 /* CONFIG_RTC */
 #define RTC_M41ST84W 1 /* Archos Recorder */
@@ -434,7 +435,7 @@
 
 #endif /* BOOTLOADER */
 
-#ifdef HAVE_USBSTACK
+#if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732)
 #define HAVE_WAKEUP_OBJECTS
 #endif
 

firmware/export/jz4740.h

@@ -1247,6 +1247,49 @@
 #define    ICDC_SR_SNCNT_BIT    0  /* Sample Number Counter */
 #define    ICDC_SR_SNCNT_MASK    (0x3fff << ICDC_SR_SNCNT_BIT)
 
+#define ICDC_CDCCR1_ELININ (1 << 29)
+#define ICDC_CDCCR1_EMIC   (1 << 28)
+#define ICDC_CDCCR1_SW1ON  (1 << 27)
+#define ICDC_CDCCR1_EADC   (1 << 26)
+#define ICDC_CDCCR1_SW2ON  (1 << 25)
+#define ICDC_CDCCR1_EDAC   (1 << 24)
+#define ICDC_CDCCR1_PDVR   (1 << 20)
+#define ICDC_CDCCR1_PDVRA  (1 << 19)
+#define ICDC_CDCCR1_VRPLD  (1 << 18)
+#define ICDC_CDCCR1_VRCGL  (1 << 17)
+#define ICDC_CDCCR1_VRCGH  (1 << 16)
+#define ICDC_CDCCR1_HPMUTE (1 << 14)
+#define ICDC_CDCCR1_HPOV0  (1 << 13)
+#define ICDC_CDCCR1_HPCG   (1 << 12)
+#define ICDC_CDCCR1_HPPLDM (1 << 11)
+#define ICDC_CDCCR1_HPPLDR (1 << 10)
+#define ICDC_CDCCR1_PDHPM  (1 << 9)
+#define ICDC_CDCCR1_PDHP   (1 << 8)
+#define ICDC_CDCCR1_SUSPD  (1 << 1)
+#define ICDC_CDCCR1_RST    (1 << 0)
+
+#define ICDC_CDCCR2_AINVOL(n) ((n & 5) << 16)
+#define ICDC_CDCCR2_SMPR(n)   ((n & 4) << 8)
+#define ICDC_CDCCR2_MICBG(n)  ((n & 2) << 4)
+#define ICDC_CDCCR2_HPVOL(n)  ((n & 2) << 0)
+
+#define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5)
+
+#define ICDC_CDCCR2_SMPR_8    (0)
+#define ICDC_CDCCR2_SMPR_11   (1)
+#define ICDC_CDCCR2_SMPR_12   (2)
+#define ICDC_CDCCR2_SMPR_16   (3)
+#define ICDC_CDCCR2_SMPR_22   (4)
+#define ICDC_CDCCR2_SMPR_24   (5)
+#define ICDC_CDCCR2_SMPR_32   (6)
+#define ICDC_CDCCR2_SMPR_44   (7)
+#define ICDC_CDCCR2_SMPR_48   (8)
+
+#define ICDC_CDCCR2_HPVOL_0   (0)
+#define ICDC_CDCCR2_HPVOL_2   (1)
+#define ICDC_CDCCR2_HPVOL_4   (2)
+#define ICDC_CDCCR2_HPVOL_6   (3)
+
 
 /*************************************************************************
  * I2C
@@ -2425,6 +2468,10 @@
 #define USB_CNTL_BURST_8    (2 << 9)
 #define USB_CNTL_BURST_16   (3 << 9)
 
+/* DMA interrupt bits */
+#define USB_INTR_DMA_BULKIN  1
+#define USB_INTR_DMA_BULKOUT 2
+
 
 //----------------------------------------------------------------------
 //

firmware/export/mipsregs.h

@@ -545,7 +545,7 @@
  */
 
 #define __read_32bit_c0_register(source, sel)				\
-({ int __res;								\
+({ unsigned int __res;								\
 	if (sel == 0)							\
 		__asm__ __volatile__(					\
 			"mfc0\t%0, " #source "\n\t"			\

firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c

@@ -59,27 +59,27 @@ void lcd_update_rect(int x, int y, int width, int height)
 {
     lcd_set_target(x, y, width, height);
     
-    REG_DMAC_DCCSR(0) = 0;
+    REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = 0;
-    REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
+    REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
-    REG_DMAC_DSAR(0) = ((unsigned int)&lcd_framebuffer[y][x]) & 0x1FFFFFFF;
+    REG_DMAC_DSAR(DMA_LCD_CHANNEL) = ((unsigned int)&lcd_framebuffer[y][x]) & 0x1FFFFFFF;
-    REG_DMAC_DTAR(0) = 0x130500B0; /* SLCD_FIFO */
+    REG_DMAC_DTAR(DMA_LCD_CHANNEL) = 0x130500B0; /* SLCD_FIFO */
-    REG_DMAC_DTCR(0) = width*height;
+    REG_DMAC_DTCR(DMA_LCD_CHANNEL) = width*height;
     
-    REG_DMAC_DCMD(0) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */
+    REG_DMAC_DCMD(DMA_LCD_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */
                        | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT);                            /* | (2 << 12) | (3 << 8) */
-    REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN);                     /* (1 << 31) | (1 << 0) */
+    REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES;                                       /* (1 << 31) */
     
     __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size */
     
     while(REG_SLCD_STATE & SLCD_STATE_BUSY);
     REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
     
-    REG_DMAC_DMACR = DMAC_DMACR_DMAE;
+    REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN;
 
-    while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) )
+    while( !(REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) )
         yield();
     
-    REG_DMAC_DMACR = 0;
+    REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN;
     
     while(REG_SLCD_STATE & SLCD_STATE_BUSY);
     REG_SLCD_CTRL = 0;

firmware/target/mips/ingenic_jz47xx/system-jz4740.c

@@ -389,6 +389,7 @@ void udelay(unsigned int usec)
                           : "0" (i)
                           );
 }
+
 void mdelay(unsigned int msec)
 {
     unsigned int i;
@@ -632,6 +633,20 @@ static void tlb_call_refill(void)
        );
 }
 
+static void dma_init(void)
+{
+    __cpm_start_dmac();
+    
+    REG_DMAC_DCCSR(0) = 0;
+    REG_DMAC_DCCSR(1) = 0;
+    REG_DMAC_DCCSR(2) = 0;
+    REG_DMAC_DCCSR(3) = 0;
+    REG_DMAC_DCCSR(4) = 0;
+    REG_DMAC_DCCSR(5) = 0;
+    
+    REG_DMAC_DMACR = (DMAC_DMACR_PR_012345 | DMAC_DMACR_DMAE);
+}
+
 extern int main(void);
 extern void except_common_entry(void);
 
@@ -660,12 +675,14 @@ void system_main(void)
         dis_irq(i);
     
     tlb_init();
+    dma_init();
     
     detect_clock();
     
+    /* Enable interrupts at core level */
     sti();
     
-    main();
+    main(); /* Shouldn't return */
     
     while(1);
 }
@@ -686,7 +703,7 @@ void power_off(void)
     /* Put system into hibernate mode */
     __rtc_clear_alarm_flag();
     __rtc_clear_hib_stat_all();
-    //__rtc_set_scratch_pattern(0x12345678);
+    /* __rtc_set_scratch_pattern(0x12345678); */
     __rtc_enable_alarm_wakeup();
     __rtc_set_hrcr_val(0xfe0);
     __rtc_set_hwfcr_val((0xFFFF << 4));

firmware/target/mips/ingenic_jz47xx/system-target.h

@@ -102,5 +102,9 @@ void mdelay(unsigned int msec);
 void power_off(void);
 void system_reboot(void);
 
-#endif /* __SYSTEM_TARGET_H_ */
+#define DMA_LCD_CHANNEL    0
+#define DMA_NAND_CHANNEL   1
+#define DMA_USB_CHANNEL    2
+#define DMA_AIC_TX_CHANNEL 3
 
+#endif /* __SYSTEM_TARGET_H_ */

firmware/thread.c

@@ -997,7 +997,7 @@ static void __attribute__((used)) _start_thread(void)
         "lw     $8,    4($9)  \n" /* Fetch thread function pointer ($8 = $t0, $9 = $t1) */
         "lw     $29,  40($9)  \n" /* Set initial sp(=$29) */
         "sw     $0,   48($9)  \n" /* Clear start address */
-        "jalr   $8            \n" /* Start the thread */
+        "jr     $8            \n" /* Start the thread */
         "nop                  \n"
         ".set at              \n"
         ".set reorder         \n"