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D2: Enable ARM cache coherency functions (eg. during codec load), which should eliminate data aborts/freezes on track changes. NOTE: The linker script reserves space at the end of DRAM for the TTB, but this is not currently used.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22595 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rob Purchase 2009-09-01 21:35:37 +00:00
parent 166606cea0
commit 19a5dfea28
5 changed files with 13 additions and 1 deletions
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3
firmware/target/arm/tcc780x/app.lds
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@ -15,7 +15,8 @@ STARTUP(target/arm/tcc780x/crt0.o)
#define STUBOFFSET 0
#endif
#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
#include "cpu.h"
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE - TTB_SIZE
#define DRAMORIG 0x20000000 + STUBOFFSET
#define ITCMORIG 0x00000000

1
firmware/target/arm/tcc780x/system-target.h
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@ -22,6 +22,7 @@
#define SYSTEM_TARGET_H
#include "system-arm.h"
#include "mmu-arm.h"
#define CPUFREQ_DEFAULT 32000000
#define CPUFREQ_NORMAL 48000000