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iRiver H100 series: Catching up on old work. Use a better way to keep playback going when switching optical output. Doesn't mess with the DMA peripheral requests to do it like before but just writes a sample to the FIFO. Would really like to reformulate interrupt scheme on Coldfire to allow DMA interrupts to be blocked specifically but not normally.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12605 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2007-03-04 21:43:35 +00:00
parent 6a3a220da1
commit 198772a6b2
1 changed files with 21 additions and 24 deletions
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45
firmware/target/coldfire/iriver/h100/spdif-h100.c
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@ -50,46 +50,43 @@ unsigned long spdif_measure_frequency(void)
/* Set the S/PDIF audio feed */ /* Set the S/PDIF audio feed */
void spdif_set_output_source(int source, bool src_on) void spdif_set_output_source(int source, bool src_on)
{ {
static const unsigned short ebu1_config[] = static const unsigned short ebu1_config[AUDIO_NUM_SOURCES+1] =
{ {
/* SCLK2, TXSRC = PDOR3, validity, normal operation */ /* SCLK2, TXSRC = PDOR3, validity, normal operation */
[AUDIO_SRC_PLAYBACK+1] = (7 << 12) | (3 << 8) | (1 << 5) | (5 << 2), [AUDIO_SRC_PLAYBACK+1] = (3 << 8) | (1 << 5) | (5 << 2),
/* Input source is EBUin1, Feed-through monitoring */ /* Input source is EBUin1, Feed-through monitoring */
[AUDIO_SRC_SPDIF+1] = (1 << 2), [AUDIO_SRC_SPDIF+1] = (1 << 2),
/* SCLK2, TXSRC = IIS1recv, validity, normal operation */ /* SCLK2, TXSRC = IIS1recv, validity, normal operation */
[AUDIO_SRC_MIC+1] = (7 << 12) | (4 << 8) | (1 << 5) | (5 << 2), [AUDIO_SRC_MIC+1] = (4 << 8) | (1 << 5) | (5 << 2),
[AUDIO_SRC_LINEIN+1] = (7 << 12) | (4 << 8) | (1 << 5) | (5 << 2), [AUDIO_SRC_LINEIN+1] = (4 << 8) | (1 << 5) | (5 << 2),
[AUDIO_SRC_FMRADIO+1] = (7 << 12) | (4 << 8) | (1 << 5) | (5 << 2), [AUDIO_SRC_FMRADIO+1] = (4 << 8) | (1 << 5) | (5 << 2),
}; };
int level; bool kick;
unsigned long playing, recording;
if ((unsigned)source >= ARRAYLEN(ebu1_config)) if ((unsigned)source >= ARRAYLEN(ebu1_config))
source = AUDIO_SRC_PLAYBACK; source = AUDIO_SRC_PLAYBACK;
spdif_source = source; spdif_source = source;
spdif_on = spdif_powered() && src_on; spdif_on = spdif_powered() && src_on;
kick = spdif_on && source == AUDIO_SRC_PLAYBACK;
level = set_irq_level(HIGHEST_IRQ_LEVEL); /* FIFO must be in reset condition to reprogram bits 15-12 */
or_l(0x800, &EBU1CONFIG);
/* Check if DMA peripheral requests are enabled */ if (kick)
playing = DCR0 & DMA_EEXT; or_l(0x800, &IIS2CONFIG); /* Have to resync IIS2 TXSRC */
recording = DCR1 & DMA_EEXT;
EBU1CONFIG = 0x800; /* Reset before reprogram */ /* Tranceiver must be powered or else monitoring will be disabled.
CLOCKSEL bits only have relevance to normal operation so just
set them always. */
EBU1CONFIG = (spdif_on ? ebu1_config[source + 1] : 0) | (7 << 12);
/* Tranceiver must be powered or else monitoring will be disabled */ if (kick && (DCR0 & DMA_EEXT)) /* only if still playing */
EBU1CONFIG = spdif_on ? ebu1_config[source + 1] : 0; {
and_l(~0x800, &IIS2CONFIG);
/* Kick-start DMAs if in progress */ PDOR3 = 0; /* A write to the FIFO kick-starts playback */
if (recording) }
DCR1 |= DMA_START;
if (playing)
DCR0 |= DMA_START;
set_irq_level(level);
} /* spdif_set_output_source */ } /* spdif_set_output_source */
/* Return the last set S/PDIF audio source */ /* Return the last set S/PDIF audio source */