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Fixed REG and REG_ADDR style macros

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@150 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Björn Stenberg 2002-04-20 13:25:58 +00:00
parent 45e9494a45
commit 191f4d22b9
6 changed files with 497 additions and 386 deletions
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34
firmware/led.c
View file

@ -22,49 +22,49 @@
#include <led.h> #include <led.h>
#define turn_on() \ #define turn_on() \
set_bit (LEDB,PBDR+1) set_bit (LEDB,PBDR_ADDR+1)
#define turn_off() \ #define turn_off() \
clear_bit (LEDB,PBDR+1) clear_bit (LEDB,PBDR_ADDR+1)
#define start_timer() \ #define start_timer() \
set_bit (2,ITUTSTR) set_bit (2,TSTR_ADDR)
#define stop_timer() \ #define stop_timer() \
clear_bit (2,ITUTSTR) clear_bit (2,TSTR_ADDR)
#define eoi(subinterrupt) \ #define eoi(subinterrupt) \
clear_bit (subinterrupt,ITUTSR2) clear_bit (subinterrupt,TSR2_ADDR)
#define set_volume(volume) \ #define set_volume(volume) \
HI(ITUGRA2) = volume & 0x7FFF GRA2 = volume & 0x7FFF
void led_set_volume (unsigned short volume) void led_set_volume (unsigned short volume)
{ {
volume <<= 10; volume <<= 10;
if (volume == 0) if (volume == 0)
led_turn_off (); led_turn_off ();
else if (volume == 0x8000) else if (volume == 0x8000)
led_turn_on (); led_turn_on ();
else else
{ {
set_volume (volume); set_volume (volume);
start_timer (); start_timer ();
} }
} }
#pragma interrupt #pragma interrupt
void IMIA2 (void) void IMIA2 (void)
{ {
turn_off (); turn_off ();
eoi (0); eoi (0);
} }
#pragma interrupt #pragma interrupt
void OVI2 (void) void OVI2 (void)
{ {
turn_on (); turn_on ();
eoi (2); eoi (2);
} }

16
firmware/led.h
View file

@ -26,21 +26,21 @@
#define LEDB 6 /* PB6 : red LED */ #define LEDB 6 /* PB6 : red LED */
static inline void led_turn_off (void) static inline void led_turn_off (void)
{ {
clear_bit (LEDB,PBDR+1); clear_bit (LEDB,PBDR+1);
clear_bit (2,ITUTSTR); clear_bit (2,TSTR_ADDR);
} }
static inline void led_turn_on (void) static inline void led_turn_on (void)
{ {
set_bit (LEDB,PBDR+1); set_bit (LEDB,PBDR+1);
set_bit (2,ITUTSTR); set_bit (2,TSTR_ADDR);
} }
static inline void led_toggle (void) static inline void led_toggle (void)
{ {
toggle_bit (LEDB,PBDR+1); toggle_bit (LEDB,PBDR+1);
} }
extern void led_set_volume (unsigned short volume); extern void led_set_volume (unsigned short volume);
extern void led_setup (void); extern void led_setup (void);

64
firmware/serial.c
View file

@ -31,54 +31,52 @@
static int serial_byte,serial_flag; static int serial_byte,serial_flag;
void serial_putc (char byte) void serial_putc (char byte)
{ {
static int i = 0; while (!(SSR1 & (1<<TDRE)));
while (!(QI(SCISSR1) & (1<<TDRE))); TDR1 = byte;
QI(SCITDR1) = byte; clear_bit(TDRE,SSR1_ADDR);
clear_bit (TDRE,SCISSR1); }
lcd_goto ((i++)%11,1); lcd_putc (byte);
}
void serial_puts (char const *string) void serial_puts (char const *string)
{ {
int byte; int byte;
while ((byte = *string++)) while ((byte = *string++))
serial_putc (byte); serial_putc (byte);
} }
int serial_getc( void ) int serial_getc( void )
{ {
int byte; int byte;
while (!serial_flag); while (!serial_flag);
byte = serial_byte; byte = serial_byte;
serial_flag = 0; serial_flag = 0;
serial_putc (byte); serial_putc (byte);
return byte; return byte;
} }
void serial_setup (int baudrate) void serial_setup (int baudrate)
{ {
QI(SCISCR1) = SCR1 = 0;
QI(SCISSR1) = SSR1 = 0;
QI(SCISMR1) = 0; SMR1 = 0;
QI(SCIBRR1) = (PHI/(32*baudrate))-1; BRR1 = (FREQ/(32*baudrate))-1;
QI(SCISCR1) = 0x70; SCR1 = 0x70;
} }
#pragma interrupt #pragma interrupt
void REI1 (void) void REI1 (void)
{ {
clear_bit (FER,SCISSR1); clear_bit (FER,SSR1_ADDR);
} }
#pragma interrupt #pragma interrupt
void RXI1 (void) void RXI1 (void)
{ {
serial_byte = QI(SCIRDR1); serial_byte = RDR1;
serial_flag = 1; serial_flag = 1;
clear_bit (RDRF,SCISSR1); clear_bit(RDRF,SSR1_ADDR);
if (serial_byte == '0') if (serial_byte == '0')
lcd_turn_off_backlight (); lcd_turn_off_backlight ();
if (serial_byte == '1') if (serial_byte == '1')
lcd_turn_on_backlight (); lcd_turn_on_backlight ();
} }

389
firmware/sh7034.h
View file

@ -22,146 +22,275 @@
#define GBR 0x00000000 #define GBR 0x00000000
#define SCISMR0 0x05FFFEC0 /* register address macros: */
#define SCIBRR0 0x05FFFEC1
#define SCISCR0 0x05FFFEC2
#define SCITDR0 0x05FFFEC3
#define SCISSR0 0x05FFFEC4
#define SCIRDR0 0x05FFFEC5
#define SCISMR1 0x05FFFEC8
#define SCIBRR1 0x05FFFEC9
#define SCISCR1 0x05FFFECA
#define SCITDR1 0x05FFFECB
#define SCISSR1 0x05FFFECC
#define SCIRDR1 0x05FFFECD
#define ADDRA 0x05FFFEE0 #define SMR0_ADDR 0x05FFFEC0
#define ADDRAH 0x05FFFEE0 #define BRR0_ADDR 0x05FFFEC1
#define ADDRAL 0x05FFFEE1 #define SCR0_ADDR 0x05FFFEC2
#define ADDRB 0x05FFFEE2 #define TDR0_ADDR 0x05FFFEC3
#define ADDRBH 0x05FFFEE2 #define SSR0_ADDR 0x05FFFEC4
#define ADDRBL 0x05FFFEE3 #define RDR0_ADDR 0x05FFFEC5
#define ADDRC 0x05FFFEE4 #define SMR1_ADDR 0x05FFFEC8
#define ADDRCH 0x05FFFEE4 #define BRR1_ADDR 0x05FFFEC9
#define ADDRCL 0x05FFFEE5 #define SCR1_ADDR 0x05FFFECA
#define ADDRD 0x05FFFEE6 #define TDR1_ADDR 0x05FFFECB
#define ADDRDH 0x05FFFEE6 #define SSR1_ADDR 0x05FFFECC
#define ADDRDL 0x05FFFEE6 #define RDR1_ADDR 0x05FFFECD
#define ADCSR 0x05FFFEE8
#define ADCR 0x05FFFEE9
#define ITUTSTR 0x05FFFF00 #define ADDRA_ADDR 0x05FFFEE0
#define ITUTSNC 0x05FFFF01 #define ADDRAH_ADDR 0x05FFFEE0
#define ITUTMDR 0x05FFFF02 #define ADDRAL_ADDR 0x05FFFEE1
#define ITUTFCR 0x05FFFF03 #define ADDRB_ADDR 0x05FFFEE2
#define ITUTCR0 0x05FFFF04 #define ADDRBH_ADDR 0x05FFFEE2
#define ITUTIOR0 0x05FFFF05 #define ADDRBL_ADDR 0x05FFFEE3
#define ITUTIER0 0x05FFFF06 #define ADDRC_ADDR 0x05FFFEE4
#define ITUTSR0 0x05FFFF07 #define ADDRCH_ADDR 0x05FFFEE4
#define ITUTCNT0 0x05FFFF08 #define ADDRCL_ADDR 0x05FFFEE5
#define ITUGRA0 0x05FFFF0A #define ADDRD_ADDR 0x05FFFEE6
#define ITUGRB0 0x05FFFF0C #define ADDRDH_ADDR 0x05FFFEE6
#define ITUTCR1 0x05FFFF0E #define ADDRDL_ADDR 0x05FFFEE6
#define ITUTIOR1 0x05FFFF0F #define ADCSR_ADDR 0x05FFFEE8
#define ITUTIER1 0x05FFFF10 #define ADCR_ADDR 0x05FFFEE9
#define ITUTSR1 0x05FFFF11
#define ITUTCNT1 0x05FFFF12
#define ITUGRA1 0x05FFFF14
#define ITUGRB1 0x05FFFF16
#define ITUTCR2 0x05FFFF18
#define ITUTIOR2 0x05FFFF19
#define ITUTIER2 0x05FFFF1A
#define ITUTSR2 0x05FFFF1B
#define ITUTCNT2 0x05FFFF1C
#define ITUGRA2 0x05FFFF1E
#define ITUGRB2 0x05FFFF20
#define ITUTCR3 0x05FFFF22
#define ITUTIOR3 0x05FFFF23
#define ITUTIER3 0x05FFFF24
#define ITUTSR3 0x05FFFF25
#define ITUTCNT3 0x05FFFF26
#define ITUGRA3 0x05FFFF28
#define ITUGRB3 0x05FFFF2A
#define ITUBRA3 0x05FFFF2C
#define ITUBRB3 0x05FFFF2E
#define ITUTOCR 0x05FFFF31
#define ITUTCR4 0x05FFFF32
#define ITUTIOR4 0x05FFFF33
#define ITUTIER4 0x05FFFF34
#define ITUTSR4 0x05FFFF35
#define ITUTCNT4 0x05FFFF36
#define ITUGRA4 0x05FFFF38
#define ITUGRB4 0x05FFFF3A
#define ITUBRA4 0x05FFFF3C
#define ITUBRB4 0x05FFFF3E
#define DMACSAR0 0x05FFFF40 #define TSTR_ADDR 0x05FFFF00
#define DMACDAR0 0x05FFFF44 #define TSNC_ADDR 0x05FFFF01
#define DMACOR 0x05FFFF48 #define TMDR_ADDR 0x05FFFF02
#define DMACTCR0 0x05FFFF4A #define TFCR_ADDR 0x05FFFF03
#define DMACCHCR0 0x05FFFF4E #define TCR0_ADDR 0x05FFFF04
#define DMACSAR1 0x05FFFF50 #define TIOR0_ADDR 0x05FFFF05
#define DMACDAR1 0x05FFFF54 #define TIER0_ADDR 0x05FFFF06
#define DMACTCR1 0x05FFFF5A #define TSR0_ADDR 0x05FFFF07
#define DMACCHCR1 0x05FFFF5E #define TCNT0_ADDR 0x05FFFF08
#define DMACSAR2 0x05FFFF60 #define GRA0_ADDR 0x05FFFF0A
#define DMACDAR2 0x05FFFF64 #define GRB0_ADDR 0x05FFFF0C
#define DMACTCR2 0x05FFFF6A #define TCR1_ADDR 0x05FFFF0E
#define DMACCHCR2 0x05FFFF6E #define TIOR1_ADDR 0x05FFFF0F
#define DMACSAR3 0x05FFFF70 #define TIER1_ADDR 0x05FFFF10
#define DMACDAR3 0x05FFFF74 #define TSR1_ADDR 0x05FFFF11
#define DMACTCR3 0x05FFFF7A #define TCNT1_ADDR 0x05FFFF12
#define DMACCHCR3 0x05FFFF7E #define GRA_ADDR1 0x05FFFF14
#define GRB1_ADDR 0x05FFFF16
#define TCR2_ADDR 0x05FFFF18
#define TIOR2_ADDR 0x05FFFF19
#define TIER2_ADDR 0x05FFFF1A
#define TSR2_ADDR 0x05FFFF1B
#define TCNT2_ADDR 0x05FFFF1C
#define GRA2_ADDR 0x05FFFF1E
#define GRB2_ADDR 0x05FFFF20
#define TCR3_ADDR 0x05FFFF22
#define TIOR3_ADDR 0x05FFFF23
#define TIER3_ADDR 0x05FFFF24
#define TSR3_ADDR 0x05FFFF25
#define TCNT3_ADDR 0x05FFFF26
#define GRA3_ADDR 0x05FFFF28
#define GRB3_ADDR 0x05FFFF2A
#define BRA3_ADDR 0x05FFFF2C
#define BRB3_ADDR 0x05FFFF2E
#define TOCR_ADDR 0x05FFFF31
#define TCR4_ADDR 0x05FFFF32
#define TIOR4_ADDR 0x05FFFF33
#define TIER4_ADDR 0x05FFFF34
#define TSR4_ADDR 0x05FFFF35
#define TCNT4_ADDR 0x05FFFF36
#define GRA4_ADDR 0x05FFFF38
#define GRB4_ADDR 0x05FFFF3A
#define BRA4_ADDR 0x05FFFF3C
#define BRB4_ADDR 0x05FFFF3E
#define INTCIPRAB 0x05FFFF84 #define SAR0_ADDR 0x05FFFF40
#define INTCIPRA 0x05FFFF84 #define DAR0_ADDR 0x05FFFF44
#define INTCIPRB 0x05FFFF86 #define OR_ADDR 0x05FFFF48
#define INTCIPRCD 0x05FFFF88 #define TCR0_ADDR 0x05FFFF4A
#define INTCIPRC 0x05FFFF88 #define CHCR0_ADDR 0x05FFFF4E
#define INTCIPRD 0x05FFFF8A #define SAR1_ADDR 0x05FFFF50
#define INTCIPRE 0x05FFFF8C #define DAR1_ADDR 0x05FFFF54
#define INTCICR 0x05FFFF8E #define TCR1_ADDR 0x05FFFF5A
#define CHCR1_ADDR 0x05FFFF5E
#define SAR2_ADDR 0x05FFFF60
#define DAR2_ADDR 0x05FFFF64
#define TCR2_ADDR 0x05FFFF6A
#define CHCR2_ADDR 0x05FFFF6E
#define SAR3_ADDR 0x05FFFF70
#define DAR3_ADDR 0x05FFFF74
#define TCR3_ADDR 0x05FFFF7A
#define CHCR3_ADDR 0x05FFFF7E
#define UBCBAR 0x05FFFF90 #define IPRA_ADDR 0x05FFFF84
#define UBCBARH 0x05FFFF90 #define IPRB_ADDR 0x05FFFF86
#define UBCBARL 0x05FFFF92 #define IPRC_ADDR 0x05FFFF88
#define UBCBAMR 0x05FFFF94 #define IPRD_ADDR 0x05FFFF8A
#define UBCBAMRH 0x05FFFF94 #define IPRE_ADDR 0x05FFFF8C
#define UBCBAMRL 0x05FFFF96 #define ICR_ADDR 0x05FFFF8E
#define UBCBBR 0x05FFFF98
#define BSCBCR 0x05FFFFA0 #define BARH_ADDR 0x05FFFF90
#define BSCWCR1 0x05FFFFA2 #define BARL_ADDR 0x05FFFF92
#define BSCWCR2 0x05FFFFA4 #define BAMRH_ADDR 0x05FFFF94
#define BSCWCR3 0x05FFFFA6 #define BAMRL_ADDR 0x05FFFF96
#define BSCDCR 0x05FFFFA8 #define BBR_ADDR 0x05FFFF98
#define BSCPCR 0x05FFFFAA
#define BSCRCR 0x05FFFFAC
#define BSCRTCSR 0x05FFFFAE
#define BSCRTCNT 0x05FFFFB0
#define BSCRTCOR 0x05FFFFB2
#define WDTTCSR 0x05FFFFB8 #define BCR_ADDR 0x05FFFFA0
#define WDTTCNT 0x05FFFFB9 #define WCR1_ADDR 0x05FFFFA2
#define WDTRSTCSR 0x05FFFFBB #define WCR2_ADDR 0x05FFFFA4
#define WCR3_ADDR 0x05FFFFA6
#define DCR_ADDR 0x05FFFFA8
#define PCR_ADDR 0x05FFFFAA
#define RCR_ADDR 0x05FFFFAC
#define RTCSR_ADDR 0x05FFFFAE
#define RTCNT_ADDR 0x05FFFFB0
#define RTCOR_ADDR 0x05FFFFB2
#define SBYCR 0x05FFFFBC #define TCSR_ADDR 0x05FFFFB8
#define TCNT_ADDR 0x05FFFFB9
#define RSTCSR_ADDR 0x05FFFFBB
#define PABDR 0x05FFFFC0 #define SBYCR_ADDR 0x05FFFFBC
#define PADR 0x05FFFFC0
#define PBDR 0x05FFFFC2 #define PADR_ADDR 0x05FFFFC0
#define PABIOR 0x05FFFFC4 #define PBDR_ADDR 0x05FFFFC2
#define PAIOR (*((volatile unsigned short *)0x05FFFFC4)) #define PAIOR_ADDR 0x05FFFFC4
#define PBIOR (*((volatile unsigned short *)0x05FFFFC6)) #define PBIOR_ADDR 0x05FFFFC6
#define PACR 0x05FFFFC8 #define PACR1_ADDR 0x05FFFFC8
#define PACR1 0x05FFFFC8 #define PACR2_ADDR 0x05FFFFCA
#define PACR2 0x05FFFFCA #define PBCR1_ADDR 0x05FFFFCC
#define PBCR 0x05FFFFCC #define PBCR2_ADDR 0x05FFFFCE
#define PBCR1 0x05FFFFCC #define PCDR_ADDR 0x05FFFFD0
#define PBCR2 0x05FFFFCE
#define PCDR 0x05FFFFD1 #define CASCR_ADDR 0x05FFFFEE
#define CASCR 0x05FFFFEE
/* register macros for direct access: */
#define SMR0 (*((volatile unsigned char*)SMR0_ADDR))
#define BRR0 (*((volatile unsigned char*)BRR0_ADDR))
#define SCR0 (*((volatile unsigned char*)SCR0_ADDR))
#define TDR0 (*((volatile unsigned char*)TDR0_ADDR))
#define SSR0 (*((volatile unsigned char*)SSR0_ADDR))
#define RDR0 (*((volatile unsigned char*)RDR0_ADDR))
#define SMR1 (*((volatile unsigned char*)SMR1_ADDR))
#define BRR1 (*((volatile unsigned char*)BRR1_ADDR))
#define SCR1 (*((volatile unsigned char*)SCR1_ADDR))
#define TDR1 (*((volatile unsigned char*)TDR1_ADDR))
#define SSR1 (*((volatile unsigned char*)SSR1_ADDR))
#define RDR1 (*((volatile unsigned char*)RDR1_ADDR))
#define ADDRA (*((volatile unsigned short*)ADDRA_ADDR))
#define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR))
#define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR))
#define ADDRB (*((volatile unsigned short*)ADDRB_ADDR))
#define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR))
#define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR))
#define ADDRC (*((volatile unsigned short*)ADDRC_ADDR))
#define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR))
#define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR))
#define ADDRD (*((volatile unsigned short*)ADDRD_ADDR))
#define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR))
#define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR))
#define ADCSR (*((volatile unsigned char*)ADCSR_ADDR))
#define ADCR (*((volatile unsigned char*)ADCR_ADDR))
#define TSTR (*((volatile unsigned char*)TSTR_ADDR))
#define TSNC (*((volatile unsigned char*)TSNC_ADDR))
#define TMDR (*((volatile unsigned char*)TMDR_ADDR))
#define TFCR (*((volatile unsigned char*)TFCR_ADDR))
#define TCR0 (*((volatile unsigned char*)TCR0_ADDR))
#define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR))
#define TIER0 (*((volatile unsigned char*)TIER0_ADDR))
#define TSR0 (*((volatile unsigned char*)TSR0_ADDR))
#define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR))
#define GRA0 (*((volatile unsigned short*)GRA0_ADDR))
#define GRB0 (*((volatile unsigned short*)GRB0_ADDR))
#define TCR1 (*((volatile unsigned char*)TCR1_ADDR))
#define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR))
#define TIER1 (*((volatile unsigned char*)TIER1_ADDR))
#define TSR1 (*((volatile unsigned char*)TSR1_ADDR))
#define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR))
#define GRA1 (*((volatile unsigned short*)GRA_ADDR))1
#define GRB1 (*((volatile unsigned short*)GRB1_ADDR))
#define TCR2 (*((volatile unsigned char*)TCR2_ADDR))
#define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR))
#define TIER2 (*((volatile unsigned char*)TIER2_ADDR))
#define TSR2 (*((volatile unsigned char*)TSR2_ADDR))
#define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR))
#define GRA2 (*((volatile unsigned short*)GRA2_ADDR))
#define GRB2 (*((volatile unsigned short*)GRB2_ADDR))
#define TCR3 (*((volatile unsigned char*)TCR3_ADDR))
#define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR))
#define TIER3 (*((volatile unsigned char*)TIER3_ADDR))
#define TSR3 (*((volatile unsigned char*)TSR3_ADDR))
#define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR))
#define GRA3 (*((volatile unsigned short*)GRA3_ADDR))
#define GRB3 (*((volatile unsigned short*)GRB3_ADDR))
#define BRA3 (*((volatile unsigned short*)BRA3_ADDR))
#define BRB3 (*((volatile unsigned short*)BRB3_ADDR))
#define TOCR (*((volatile unsigned char*)TOCR_ADDR))
#define TCR4 (*((volatile unsigned char*)TCR4_ADDR))
#define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR))
#define TIER4 (*((volatile unsigned char*)TIER4_ADDR))
#define TSR4 (*((volatile unsigned char*)TSR4_ADDR))
#define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR))
#define GRA4 (*((volatile unsigned short*)GRA4_ADDR))
#define GRB4 (*((volatile unsigned short*)GRB4_ADDR))
#define BRA4 (*((volatile unsigned short*)BRA4_ADDR))
#define BRB4 (*((volatile unsigned short*)BRB4_ADDR))
#define SAR0 (*((volatile unsigned long*)SAR0_ADDR))
#define DAR0 (*((volatile unsigned long*)DAR0_ADDR))
#define DMAOR (*((volatile unsigned long*)DMAOR_ADDR))
#define TCR0 (*((volatile unsigned long*)TCR0_ADDR))
#define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR))
#define SAR1 (*((volatile unsigned long*)SAR1_ADDR))
#define DAR1 (*((volatile unsigned long*)DAR1_ADDR))
#define TCR1 (*((volatile unsigned long*)TCR1_ADDR))
#define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR))
#define SAR2 (*((volatile unsigned long*)SAR2_ADDR))
#define DAR2 (*((volatile unsigned long*)DAR2_ADDR))
#define TCR2 (*((volatile unsigned long*)TCR2_ADDR))
#define HCR2 (*((volatile unsigned short*)CHCR2_ADDR))
#define SAR3 (*((volatile unsigned long*)SAR3_ADDR))
#define DAR3 (*((volatile unsigned long*)DAR3_ADDR))
#define TCR3 (*((volatile unsigned long*)TCR3_ADDR))
#define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR))
#define IPRA (*((volatile unsigned short*)IPRA_ADDR))
#define IPRB (*((volatile unsigned short*)IPRB_ADDR))
#define IPRC (*((volatile unsigned short*)IPRC_ADDR))
#define IPRD (*((volatile unsigned short*)IPRD_ADDR))
#define IPRE (*((volatile unsigned short*)IPRE_ADDR))
#define ICR (*((volatile unsigned short*)ICR_ADDR))
#define BARH (*((volatile unsigned short*)BARH_ADDR))
#define BARL (*((volatile unsigned short*)BARL_ADDR))
#define BAMRH (*((volatile unsigned short*)BAMRH_ADDR))
#define BAMRL (*((volatile unsigned short*)BAMRL_ADDR))
#define BBR (*((volatile unsigned short*)BBR_ADDR))
#define BCR (*((volatile unsigned short*)BCR_ADDR))
#define WCR1 (*((volatile unsigned short*)WCR1_ADDR))
#define WCR2 (*((volatile unsigned short*)WCR2_ADDR))
#define WCR3 (*((volatile unsigned short*)WCR3_ADDR))
#define DCR (*((volatile unsigned short*)DCR_ADDR))
#define PCR (*((volatile unsigned short*)PCR_ADDR))
#define RCR (*((volatile unsigned short*)RCR_ADDR))
#define RTCSR (*((volatile unsigned short*)RTCSR_ADDR))
#define RTCNT (*((volatile unsigned short*)RTCNT_ADDR))
#define RTCOR (*((volatile unsigned short*)RTCOR_ADDR))
#define TCSR (*((volatile unsigned char*)TCSR_ADDR))
#define TCNT (*((volatile unsigned char*)TCNT_ADDR))
#define RSTCSR (*((volatile unsigned char*)RSTCSR_ADDR))
#define SBYCR (*((volatile unsigned char*)SBYCR_ADDR))
#define PADR (*((volatile unsigned short*)PADR_ADDR))
#define PBDR (*((volatile unsigned short*)PBDR_ADDR))
#define PAIOR (*((volatile unsigned short*)PAIOR_ADDR))
#define PBIOR (*((volatile unsigned short*)PBIOR_ADDR))
#define PACR1 (*((volatile unsigned short*)PACR1_ADDR))
#define PACR2 (*((volatile unsigned short*)PACR2_ADDR))
#define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR))
#define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR))
#define PCDR (*((volatile unsigned short*)PCDR_ADDR))
#define CASCR (*((volatile unsigned char*)CASCR_ADDR))
#endif #endif

359
firmware/system.c
View file

@ -142,166 +142,169 @@ reserve_interrupt ( 108);
default_interrupt (ADITI, 109); default_interrupt (ADITI, 109);
void (*vbr[]) (void) __attribute__ ((section (".sram.vbr"))) = void (*vbr[]) (void) __attribute__ ((section (".sram.vbr"))) =
{ {
/*** 0-1 Power-on Reset ***/ /*** 0-1 Power-on Reset ***/
reset_pc,reset_sp, reset_pc,reset_sp,
/*** 2-3 Manual Reset ***/ /*** 2-3 Manual Reset ***/
reset_pc,reset_sp, reset_pc,reset_sp,
/*** 4 General Illegal Instruction ***/ /*** 4 General Illegal Instruction ***/
GII, GII,
/*** 5 Reserved ***/ /*** 5 Reserved ***/
UIE5, UIE5,
/*** 6 Illegal Slot Instruction ***/ /*** 6 Illegal Slot Instruction ***/
ISI, ISI,
/*** 7-8 Reserved ***/ /*** 7-8 Reserved ***/
UIE7,UIE8, UIE7,UIE8,
/*** 9 CPU Address Error ***/ /*** 9 CPU Address Error ***/
CPUAE, CPUAE,
/*** 10 DMA Address Error ***/ /*** 10 DMA Address Error ***/
DMAAE, DMAAE,
/*** 11 NMI ***/ /*** 11 NMI ***/
NMI, NMI,
/*** 12 User Break ***/ /*** 12 User Break ***/
UB, UB,
/*** 13-31 Reserved ***/ /*** 13-31 Reserved ***/
UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31, UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
/*** 32-63 TRAPA #20...#3F ***/ /*** 32-63 TRAPA #20...#3F ***/
TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63, TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
/*** 64-71 IRQ0-7 ***/ /*** 64-71 IRQ0-7 ***/
IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7, IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
/*** 72 DMAC0 ***/ /*** 72 DMAC0 ***/
DEI0, DEI0,
/*** 73 Reserved ***/ /*** 73 Reserved ***/
UIE73, UIE73,
/*** 74 DMAC1 ***/ /*** 74 DMAC1 ***/
DEI1, DEI1,
/*** 75 Reserved ***/ /*** 75 Reserved ***/
UIE75, UIE75,
/*** 76 DMAC2 ***/ /*** 76 DMAC2 ***/
DEI2, DEI2,
/*** 77 Reserved ***/ /*** 77 Reserved ***/
UIE77, UIE77,
/*** 78 DMAC3 ***/ /*** 78 DMAC3 ***/
DEI3, DEI3,
/*** 79 Reserved ***/ /*** 79 Reserved ***/
UIE79, UIE79,
/*** 80-82 ITU0 ***/ /*** 80-82 ITU0 ***/
IMIA0,IMIB0,OVI0, IMIA0,IMIB0,OVI0,
/*** 83 Reserved ***/ /*** 83 Reserved ***/
UIE83, UIE83,
/*** 84-86 ITU1 ***/ /*** 84-86 ITU1 ***/
IMIA1,IMIB1,OVI1, IMIA1,IMIB1,OVI1,
/*** 87 Reserved ***/ /*** 87 Reserved ***/
UIE87, UIE87,
/*** 88-90 ITU2 ***/ /*** 88-90 ITU2 ***/
IMIA2,IMIB2,OVI2, IMIA2,IMIB2,OVI2,
/*** 91 Reserved ***/ /*** 91 Reserved ***/
UIE91, UIE91,
/*** 92-94 ITU3 ***/ /*** 92-94 ITU3 ***/
IMIA3,IMIB3,OVI3, IMIA3,IMIB3,OVI3,
/*** 95 Reserved ***/ /*** 95 Reserved ***/
UIE95, UIE95,
/*** 96-98 ITU4 ***/ /*** 96-98 ITU4 ***/
IMIA4,IMIB4,OVI4, IMIA4,IMIB4,OVI4,
/*** 99 Reserved ***/ /*** 99 Reserved ***/
UIE99, UIE99,
/*** 100-103 SCI0 ***/ /*** 100-103 SCI0 ***/
REI0,RXI0,TXI0,TEI0, REI0,RXI0,TXI0,TEI0,
/*** 104-107 SCI1 ***/ /*** 104-107 SCI1 ***/
REI1,RXI1,TXI1,TEI1, REI1,RXI1,TXI1,TEI1,
/*** 108 Parity Control Unit ***/ /*** 108 Parity Control Unit ***/
UIE108, UIE108,
/*** 109 AD Converter ***/ /*** 109 AD Converter ***/
ADITI ADITI
}; };
void system_reboot (void) void system_reboot (void)
{ {
cli (); cli ();
asm volatile ("ldc\t%0,vbr" : : "r"(0)); asm volatile ("ldc\t%0,vbr" : : "r"(0));
SI(INTCIPRAB) = IPRA = 0;
SI(INTCIPRCD) = 0; IPRB = 0;
HI(INTCIPRE) = IPRC = 0;
HI(INTCICR) = 0; IPRD = 0;
IPRE = 0;
ICR = 0;
asm volatile ("jmp @%0; mov.l @%1,r15" : : "r"(SI(0)),"r"(4)); asm volatile ("jmp @%0; mov.l @%1,r15" : :
} "r"(*(char*)0),"r"(4));
}
void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */ void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
{ {
unsigned int i,n; unsigned int i,n;
lcd_stop (); lcd_stop ();
asm volatile ("sts\tpr,%0" : "=r"(n)); asm volatile ("sts\tpr,%0" : "=r"(n));
@ -314,121 +317,121 @@ void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
lcd_stop (); lcd_stop ();
while (1) while (1)
{ {
led_toggle (); led_toggle ();
for (i = 0; i < 240000; ++i); for (i = 0; i < 240000; ++i);
} }
} }
asm ( asm (
"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n" "_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4"); "_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");

21
firmware/system.h
View file

@ -21,36 +21,17 @@
#define __SYSTEM_H__ #define __SYSTEM_H__
#include <sh7034.h> #include <sh7034.h>
#define KB *1024
#define MB *1024 KB
#define GB *1024 MB
#define Hz *1
#define KHz *1000 Hz
#define MHz *1000 KHz
#define ns *1
#define us *1000 ns
#define ms *1000 us
/* /*
* 11.059,200 MHz => 90.4224537037037037037037037037037... ns * 11.059,200 MHz => 90.4224537037037037037037037037037... ns
* 12.000,000 MHz => 83.3333333333333333333333333333333... ns * 12.000,000 MHz => 83.3333333333333333333333333333333... ns
*/ */
#define PHI ((int)(12.000000 MHz)) #define FREQ 12000000
#define BAUDRATE 9600 #define BAUDRATE 9600
//#define PHI ((int)(11.059200 MHz)) //#define PHI ((int)(11.059200 MHz))
//#define BAUDRATE 115200 /* 115200 - 9600 */ //#define BAUDRATE 115200 /* 115200 - 9600 */
#define SI(a) \
(*((volatile int *)a)) /* single integer access - 32-bit */
#define HI(a) \
(*((volatile short *)a)) /* half integer access - 16-bit */
#define QI(a) \
(*((volatile char *)a)) /* quarter integer access - 8-bit */
#define nop \ #define nop \
asm volatile ("nop") asm volatile ("nop")