forked from len0rd/rockbox
Some more replacing of inl/outl with register #define's (doesn't change end-result binary). Add lots more #define's based on the ipodlinux wiki and some extrapolation.
Also add PortalPlayer SoC version to the HW info debug screen. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12575 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Barry Wardell
parent
8b061252c4
commit
169ebdbda7
4 changed files with 116 additions and 31 deletions
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@ -582,6 +582,12 @@ static bool dbg_hw_info(void)
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snprintf(buf, sizeof(buf), "HW rev: 0x%08x", ipod_hw_rev);
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lcd_puts(0, 1, buf);
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char pp_version[] = { (PP_VER2 >> 24) & 0xff, (PP_VER2 >> 16) & 0xff,
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(PP_VER2 >> 8) & 0xff, (PP_VER2) & 0xff,
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(PP_VER1 >> 24) & 0xff, (PP_VER1 >> 16) & 0xff,
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(PP_VER1 >> 8) & 0xff, (PP_VER1) & 0xff, '\0' };
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snprintf(buf, sizeof(buf), "PP version: %s", pp_version);
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lcd_puts(0, 2, buf);
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lcd_update();
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while(1)
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@ -31,30 +31,71 @@
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#define PROC_ID_COP 0xaa
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/* Interrupts */
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#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
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#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
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#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
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#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
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#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000))
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#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100))
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#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000))
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#define COP_INT_STAT (*(volatile unsigned long*)(0x60004004))
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#define CPU_FIQ_STAT (*(volatile unsigned long*)(0x60004008))
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#define COP_FIQ_STAT (*(volatile unsigned long*)(0x6000400c))
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#define INT_STAT (*(volatile unsigned long*)(0x60004010))
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#define INT_FORCED_STAT (*(volatile unsigned long*)(0x60004014))
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#define INT_FORCED_SET (*(volatile unsigned long*)(0x60004018))
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#define INT_FORCED_CLR (*(volatile unsigned long*)(0x6000401c))
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#define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020))
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#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
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#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
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#define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c))
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#define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030))
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#define COP_INT_EN (*(volatile unsigned long*)(0x60004034))
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#define COP_INT_CLR (*(volatile unsigned long*)(0x60004038))
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#define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c))
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#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100))
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#define COP_HI_INT_STAT (*(volatile unsigned long*)(0x60004104))
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#define CPU_HI_FIQ_STAT (*(volatile unsigned long*)(0x60004108))
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#define COP_HI_FIQ_STAT (*(volatile unsigned long*)(0x6000410c))
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#define HI_INT_STAT (*(volatile unsigned long*)(0x60004110))
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#define HI_INT_FORCED_STAT (*(volatile unsigned long*)(0x60004114))
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#define HI_INT_FORCED_SET (*(volatile unsigned long*)(0x60004118))
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#define HI_INT_FORCED_CLR (*(volatile unsigned long*)(0x6000411c))
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#define CPU_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004120))
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#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
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#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
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#define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
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#define COP_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004130))
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#define COP_HI_INT_EN (*(volatile unsigned long*)(0x60004134))
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#define COP_HI_INT_CLR (*(volatile unsigned long*)(0x60004138))
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#define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
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#define TIMER1_IRQ 0
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#define TIMER2_IRQ 1
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#define MAILBOX_IRQ 4
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#define I2S_IRQ 10
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#define IDE_IRQ 23
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#define USB_IRQ 24
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#define FIREWIRE_IRQ 25
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#define HI_IRQ 30
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#define GPIO_IRQ (32+0)
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#define SER0_IRQ (32+4)
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#define SER1_IRQ (32+5)
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#define I2C_IRQ (32+8)
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#define TIMER1_MASK (1 << TIMER1_IRQ)
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#define TIMER2_MASK (1 << TIMER2_IRQ)
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#define I2S_MASK (1 << I2S_IRQ)
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#define IDE_MASK (1 << IDE_IRQ)
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#define GPIO_MASK (1 << (GPIO_IRQ-32))
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#define SER0_MASK (1 << (SER0_IRQ-32))
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#define SER1_MASK (1 << (SER1_IRQ-32))
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#define I2C_MASK (1 << (I2C_IRQ-32))
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#define TIMER1_MASK (1 << TIMER1_IRQ)
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#define TIMER2_MASK (1 << TIMER2_IRQ)
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#define MAILBOX_MASK (1 << MAILBOX_IRQ)
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#define I2S_MASK (1 << I2S_IRQ)
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#define IDE_MASK (1 << IDE_IRQ)
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#define USB_MASK (1 << USB_IRQ)
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#define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
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#define HI_MASK (1 << HI_IRQ)
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#define GPIO_MASK (1 << (GPIO_IRQ-32))
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#define SER0_MASK (1 << (SER0_IRQ-32))
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#define SER1_MASK (1 << (SER1_IRQ-32))
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#define I2C_MASK (1 << (I2C_IRQ-32))
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/* Timers */
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#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000))
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@ -62,14 +103,22 @@
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#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008))
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#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c))
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#define USEC_TIMER (*(volatile unsigned long *)(0x60005010))
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#define RTC (*(volatile unsigned long *)(0x60005014))
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/* Device Controller */
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#define DEV_RS (*(volatile unsigned long *)(0x60006004))
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#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
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#define DEV_SYSTEM 0x4
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#define DEV_I2C 0x1000
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#define DEV_USB 0x400000
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#define DEV_SYSTEM 0x4
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#define DEV_SER0 0x40
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#define DEV_SER1 0x80
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#define DEV_I2S 0x800
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#define DEV_I2C 0x1000
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#define DEV_OPTO 0x10000
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#define DEV_PIEZO 0x10000
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#define DEV_USB 0x400000
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#define DEV_FIREWIRE 0x800000
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#define DEV_IDE0 0x2000000
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/* Processors Control */
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#define CPU_CTL (*(volatile unsigned long *)(0x60007000))
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@ -186,12 +235,11 @@
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#define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c))
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/* Device initialization */
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#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
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#define PP_VER1 (*(volatile unsigned long *)(0x70000000))
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#define PP_VER2 (*(volatile unsigned long *)(0x70000004))
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#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
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#define INIT_USB 0x80000000
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/* I2C */
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#define I2C_BASE 0x7000c000
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#define INIT_USB 0x80000000
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/* I2S */
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#define IISCONFIG (*(volatile unsigned long*)(0x70002800))
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@ -199,10 +247,40 @@
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#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
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#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
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/* Serial Controller */
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#define SERIAL0 (*(volatile unsigned long*)(0x70006000))
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#define SERIAL1 (*(volatile unsigned long*)(0x70006040))
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/* I2C */
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#define I2C_BASE 0x7000c000
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/* EIDE Controller */
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#define IDE0_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000000))
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#define IDE0_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000004))
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#define IDE0_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000008))
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#define IDE0_SEC_TIMING1 (*(volatile unsigned long*)(0xc300000c))
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#define IDE1_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000010))
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#define IDE1_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000014))
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#define IDE1_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000018))
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#define IDE1_SEC_TIMING1 (*(volatile unsigned long*)(0xc300001c))
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#define IDE0_CFG (*(volatile unsigned long*)(0xc3000028))
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#define IDE1_CFG (*(volatile unsigned long*)(0xc300002c))
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#define IDE0_CNTRLR_STAT (*(volatile unsigned long*)(0xc30001e0))
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/* USB controller */
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#define USB_BASE 0xc5000000
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#define USB_BASE 0xc5000000
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/* Firewire Controller */
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#define FIREWIRE_BASE 0xc6000000
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/* Memory controller */
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#define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
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#define CACHE_INIT_BASE (*(volatile unsigned long*)(0xf0004000))
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#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
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#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
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#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
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@ -211,5 +289,7 @@
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#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
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#define CACHE_CTRL1 (*(volatile unsigned long*)(0xf000f020))
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#define CACHE_CTRL2 (*(volatile unsigned long*)(0xf000f024))
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#endif
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@ -43,9 +43,9 @@ bool ata_is_coldstart()
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void ata_device_init()
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{
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/* From ipod-ide.c:ipod_ide_register() */
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outl(inl(0xc3000028) | (1 << 5), 0xc3000028);
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outl(inl(0xc3000028) & ~0x10000000, 0xc3000028);
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IDE0_CFG |= (1<<5);
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IDE0_CFG &=~(0x10000000); /* cpu < 65MHz */
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outl(0x10, 0xc3000000);
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outl(0x80002150, 0xc3000004);
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IDE0_PRI_TIMING0 = 0x10;
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IDE0_PRI_TIMING1 = 0x80002150;
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}
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@ -206,9 +206,8 @@ void pcm_play_dma_start(const void *addr, size_t size)
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pcm_playing = true;
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#if CONFIG_CPU == PP5020
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/* setup I2S interrupt for FIQ */
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outl(inl(0x6000402c) | I2S_MASK, 0x6000402c);
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CPU_INT_EN = I2S_MASK;
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CPU_INT_PRIORITY |= I2S_MASK; /* FIQ priority for I2S */
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CPU_INT_EN = I2S_MASK; /* Enable I2S interrupt */
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#elif CONFIG_CPU == PP5024
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#else
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/* setup I2S interrupt for FIQ */
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