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S5L8702: Reallocate the bootloader without dependency on _dfuloadaddr

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Also adds support for S5L8720 initialization.

This currently changes only the bootloader code for ipod6g. Tested on target.

This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.

Credit: Cástor Muñoz <cmvidal@gmail.com>
Change-Id: Ib4b5f12b701058940c1c5bd686d8ac346ae14e12
This commit is contained in:
Vencislav Atanasov 2024-12-12 23:27:14 +02:00 • committed by Solomon Peachy
parent e9b0aa495b
commit 0fef17206e
1 changed files with 54 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

64
firmware/target/arm/s5l8702/crt0.S
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@ -38,31 +38,56 @@ start:
ldr pc, =fiq_handler
.ltorg
_newstart:
#if !defined(BOOTLOADER)
ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
#ifndef BOOTLOADER
/* we do not want to execute from 0x0 as iram will be mapped there */
ldr pc, =newstart2
.section .init.text,"ax",%progbits
newstart2:
#endif
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
#ifdef BOOTLOADER
/* Relocate ourself to IRAM1 - we have been loaded to IRAM0 */
ldr r0, =_dfuloadaddr
ldr r1, =_movestart
ldr r2, =_moveend
/* Actually we are reallocating from load address IRAM0:0000 or
* IRAM1:0000 to exec address IRAM1:0800.
* Note that vector section is also reallocated to IRAM0:0000.
*/
/* Reallocate from IRAM0:0000 or IRAM1:0000 to IRAM1:0800 */
/* _movestart and _moveend must be already aligned to 32-byte */
_rtpc:
sub r11, pc, #8 /* subtract 8 for pipeline */
sub r11, #_rtpc-start /* _src_start = runtime start: address */
/* [start .. start+_movelen] -> [_movestart .. _moveend] */
ldr r1, =_moveend
ldr r2, =_movestart
sub r3, r1, r2 /* _movelen = _moveend - _movestart */
add r0, r11, r3 /* _src_end = _src_start + _movelen */
1:
ldmdb r0!, {r3-r10}
stmdb r1!, {r3-r10}
cmp r2, r1
blt 1b
/* copy vector section to start of IRAM0 (it will be mapped to 0x0) */
/* [start .. _newstart] -> [IRAM0_START .. IRAM0_START+vect_len] */
mov r0, r11 // src start
ldr r1, =IRAM0_ORIG // dst start
add r2, r1, #_newstart-start // dst end
2:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r1, r2
blt 1b
blt 2b
ldr pc, =start_loc /* jump to the relocated start_loc: */
.section .init.text,"ax",%progbits
.global start_loc
start_loc:
#endif
#endif /* BOOTLOADER */
#if defined(IPOD_6G) || defined(IPOD_NANO3G)
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000
bic r0, r0, #0x5
@ -75,7 +100,26 @@ start_loc:
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
/* reset VIC controller */
#elif defined(IPOD_NANO4G)
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000
bic r0, r0, #0x5
mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
mov r0, #0
mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate dcache */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffer */
mcr p15, 0, r0, c8, c7, 0 /* invalidate all unlocked entries in TLB */
mcr p15, 0, r0, c13, c0, 0 /* disable context id register */
/* XXX: arm1176jaf page 249/972 */
// TODO: put it in mmu-armv6.S
// mcr p15, 0, r0, c2, c0, 2 /* write translation table control register (set backwards compatiblity) */
#endif
/* reset VIC controller */ // TODO: this could go to system_init()
ldr r1, =0x38e00000
add r2, r1, #0x00001000
add r3, r1, #0x00002000
@ -86,7 +130,7 @@ start_loc:
str r4, [r2,#0xf00]
str r4, [r3,#0x08]
str r4, [r3,#0x0c]
str r0, [r1,#0x14]
str r0, [r1,#0x14] // TODO: This is not done by s5l8720, and I don't think it's necessary for s5l8702
str r0, [r2,#0x14]
#if defined(BOOTLOADER)