forked from len0rd/rockbox
Correct svn:keywords and svn:eol-style on a few more files.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21798 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Thomas Martitz
parent
467999ac9c
commit
0dd0e4e072
14 changed files with 190 additions and 190 deletions
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: wm8975.c 13453 2007-05-20 23:10:15Z christian $
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* $Id$
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*
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*
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* Driver for MAS35xx audio codec
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* Driver for MAS35xx audio codec
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*
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*
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: usb-mr500.c 18487 2008-09-10 20:14:22Z bertrik $
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* $Id$
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*
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*
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* Copyright (C) 2009 by Karl Kurbjun
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* Copyright (C) 2009 by Karl Kurbjun
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* Portions Copyright (C) 2007 by Catalin Patulea
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* Portions Copyright (C) 2007 by Catalin Patulea
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@ -5,7 +5,7 @@
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: ramdisk.c 18965 2008-11-01 17:33:21Z gevaerts $
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* $Id$
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*
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*
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* Copyright (C) 2008 Frank Gevaerts
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* Copyright (C) 2008 Frank Gevaerts
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*
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*
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@ -5,7 +5,7 @@
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: rtc_as3514.c 12131 2007-01-27 20:48:48Z dan_a $
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* $Id$
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*
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*
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* Copyright (C) 2007 by Barry Wardell
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* Copyright (C) 2007 by Barry Wardell
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*
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*
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@ -5,7 +5,7 @@
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: rtc_as3514.c 12131 2007-01-27 20:48:48Z dan_a $
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* $Id$
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*
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*
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* Copyright (C) 2007 by Jonathan Gordon
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* Copyright (C) 2007 by Jonathan Gordon
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*
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*
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: $
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* $Id$
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*
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*
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* Copyright (C) 2007 by Jonathan Gordon
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* Copyright (C) 2007 by Jonathan Gordon
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*
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*
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@ -114,7 +114,7 @@
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#define DBOP_TIMPOL_23 (*(volatile unsigned long *)(DBOP_BASE + 0x04))
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#define DBOP_TIMPOL_23 (*(volatile unsigned long *)(DBOP_BASE + 0x04))
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#define DBOP_CTRL (*(volatile unsigned long *)(DBOP_BASE + 0x08))
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#define DBOP_CTRL (*(volatile unsigned long *)(DBOP_BASE + 0x08))
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#define DBOP_STAT (*(volatile unsigned long *)(DBOP_BASE + 0x0C))
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#define DBOP_STAT (*(volatile unsigned long *)(DBOP_BASE + 0x0C))
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#define DBOP_DOUT (*(volatile unsigned short*)(DBOP_BASE + 0x10))
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#define DBOP_DOUT (*(volatile unsigned short *)(DBOP_BASE + 0x10))
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#define DBOP_DIN (*(volatile unsigned short*)(DBOP_BASE + 0x14))
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#define DBOP_DIN (*(volatile unsigned short*)(DBOP_BASE + 0x14))
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id: iap.h 17400 2008-05-07 20:22:16Z xxxxxx $
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* $Id$
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*
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*
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* Copyright (C) 2002 by Alan Korr
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* Copyright (C) 2002 by Alan Korr
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*
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*
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@ -1,181 +1,181 @@
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/***************************************************************************
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/***************************************************************************
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* __________ __ ___.
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* \/ \/ \/ \/ \/
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* $Id$
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* $Id$
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*
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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*
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* This program is free software; you can redistribute it and/or
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* of the License, or (at your option) any later version.
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*
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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* KIND, either express or implied.
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*
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*
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****************************************************************************/
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****************************************************************************/
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#ifndef ISP1583_H
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#ifndef ISP1583_H
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#define ISP1583_H
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#define ISP1583_H
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#include "usb-target.h"
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#include "usb-target.h"
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#ifndef ISP1583_H_OVERRIDE
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#ifndef ISP1583_H_OVERRIDE
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/* Initialization registers */
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/* Initialization registers */
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#define ISP1583_INIT_ADDRESS (*((volatile unsigned char*)(ISP1583_IOBASE+0x0)))
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#define ISP1583_INIT_ADDRESS (*((volatile unsigned char*)(ISP1583_IOBASE+0x0)))
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#define ISP1583_INIT_MODE (*((volatile unsigned short*)(ISP1583_IOBASE+0xC)))
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#define ISP1583_INIT_MODE (*((volatile unsigned short*)(ISP1583_IOBASE+0xC)))
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#define ISP1583_INIT_INTCONF (*((volatile unsigned char*)(ISP1583_IOBASE+0x10)))
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#define ISP1583_INIT_INTCONF (*((volatile unsigned char*)(ISP1583_IOBASE+0x10)))
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#define ISP1583_INIT_OTG (*((volatile unsigned char*)(ISP1583_IOBASE+0x12)))
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#define ISP1583_INIT_OTG (*((volatile unsigned char*)(ISP1583_IOBASE+0x12)))
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#define ISP1583_INIT_INTEN_A (*((volatile unsigned long*)(ISP1583_IOBASE+0x14)))
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#define ISP1583_INIT_INTEN_A (*((volatile unsigned long*)(ISP1583_IOBASE+0x14)))
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#define ISP1583_INIT_INTEN_B
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#define ISP1583_INIT_INTEN_B
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#define ISP1583_INIT_INTEN_READ ISP1583_INIT_INTEN_A
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#define ISP1583_INIT_INTEN_READ ISP1583_INIT_INTEN_A
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/* Data Flow registers */
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/* Data Flow registers */
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#define ISP1583_DFLOW_EPINDEX (*((volatile unsigned char*)(ISP1583_IOBASE+0xC2)))
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#define ISP1583_DFLOW_EPINDEX (*((volatile unsigned char*)(ISP1583_IOBASE+0xC2)))
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#define ISP1583_DFLOW_CTRLFUN (*((volatile unsigned char*)(ISP1583_IOBASE+0x28)))
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#define ISP1583_DFLOW_CTRLFUN (*((volatile unsigned char*)(ISP1583_IOBASE+0x28)))
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#define ISP1583_DFLOW_DATA (*((volatile unsigned short*)(ISP1583_IOBASE+0x20)))
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#define ISP1583_DFLOW_DATA (*((volatile unsigned short*)(ISP1583_IOBASE+0x20)))
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#define ISP1583_DFLOW_BUFLEN (*((volatile unsigned short*)(ISP1583_IOBASE+0x1C)))
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#define ISP1583_DFLOW_BUFLEN (*((volatile unsigned short*)(ISP1583_IOBASE+0x1C)))
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#define ISP1583_DFLOW_BUFSTAT (*((volatile unsigned char*)(ISP1583_IOBASE+0x1E)))
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#define ISP1583_DFLOW_BUFSTAT (*((volatile unsigned char*)(ISP1583_IOBASE+0x1E)))
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#define ISP1583_DFLOW_MAXPKSZ (*((volatile unsigned short*)(ISP1583_IOBASE+0x04)))
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#define ISP1583_DFLOW_MAXPKSZ (*((volatile unsigned short*)(ISP1583_IOBASE+0x04)))
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#define ISP1583_DFLOW_EPTYPE (*((volatile unsigned short*)(ISP1583_IOBASE+0x08)))
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#define ISP1583_DFLOW_EPTYPE (*((volatile unsigned short*)(ISP1583_IOBASE+0x08)))
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/* DMA registers */
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/* DMA registers */
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#define ISP1583_DMA_ENDPOINT (*((volatile unsigned char*)(ISP1583_IOBASE+0x58)))
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#define ISP1583_DMA_ENDPOINT (*((volatile unsigned char*)(ISP1583_IOBASE+0x58)))
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/* General registers */
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/* General registers */
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#define ISP1583_GEN_INT_A (*((volatile unsigned long*)(ISP1583_IOBASE+0x18)))
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#define ISP1583_GEN_INT_A (*((volatile unsigned long*)(ISP1583_IOBASE+0x18)))
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#define ISP1583_GEN_INT_B
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#define ISP1583_GEN_INT_B
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#define ISP1583_GEN_INT_READ ISP1583_GEN_INT_A
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#define ISP1583_GEN_INT_READ ISP1583_GEN_INT_A
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#define ISP1583_GEN_CHIPID (*((volatile unsigned long*)(ISP1583_IOBASE+0x70))) /* Size=3 bytes */
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#define ISP1583_GEN_CHIPID (*((volatile unsigned long*)(ISP1583_IOBASE+0x70))) /* Size=3 bytes */
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#define ISP1583_GEN_FRAMEN0 (*((volatile unsigned short*)(ISP1583_IOBASE+0x74)))
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#define ISP1583_GEN_FRAMEN0 (*((volatile unsigned short*)(ISP1583_IOBASE+0x74)))
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#define ISP1583_GEN_SCRATCH (*((volatile unsigned short*)(ISP1583_IOBASE+0x78)))
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#define ISP1583_GEN_SCRATCH (*((volatile unsigned short*)(ISP1583_IOBASE+0x78)))
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#define ISP1583_GEN_UNLCKDEV (*((volatile unsigned short*)(ISP1583_IOBASE+0x7C)))
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#define ISP1583_GEN_UNLCKDEV (*((volatile unsigned short*)(ISP1583_IOBASE+0x7C)))
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#define ISP1583_GEN_TSTMOD (*((volatile unsigned char*)(ISP1583_IOBASE+0x84)))
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#define ISP1583_GEN_TSTMOD (*((volatile unsigned char*)(ISP1583_IOBASE+0x84)))
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#define set_int_value(a,b,value) (a) = (value);
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#define set_int_value(a,b,value) (a) = (value);
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#endif
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#endif
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#define ISP1583_UNLOCK_CODE ((unsigned short)0xAA37)
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#define ISP1583_UNLOCK_CODE ((unsigned short)0xAA37)
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/* Initialization registers' bits */
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/* Initialization registers' bits */
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/* Initialization OTG register bits */
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/* Initialization OTG register bits */
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#define INIT_OTG_BSESS_VALID (1 << 4)
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#define INIT_OTG_BSESS_VALID (1 << 4)
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/* Initialization Mode register bits */
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/* Initialization Mode register bits */
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#define INIT_MODE_TEST2 (1 << 15)
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#define INIT_MODE_TEST2 (1 << 15)
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#define INIT_MODE_TEST1 (1 << 14)
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#define INIT_MODE_TEST1 (1 << 14)
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#define INIT_MODE_TEST0 (1 << 13)
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#define INIT_MODE_TEST0 (1 << 13)
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#define INIT_MODE_DMA_CLKON (1 << 9)
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#define INIT_MODE_DMA_CLKON (1 << 9)
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#define INIT_MODE_VBUSSTAT (1 << 8)
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#define INIT_MODE_VBUSSTAT (1 << 8)
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#define INIT_MODE_CLKAON (1 << 7)
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#define INIT_MODE_CLKAON (1 << 7)
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#define INIT_MODE_SNDRSU (1 << 6)
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#define INIT_MODE_SNDRSU (1 << 6)
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#define INIT_MODE_GOSUSP (1 << 5)
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#define INIT_MODE_GOSUSP (1 << 5)
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#define INIT_MODE_SFRESET (1 << 4)
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#define INIT_MODE_SFRESET (1 << 4)
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#define INIT_MODE_GLINTENA (1 << 3)
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#define INIT_MODE_GLINTENA (1 << 3)
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#define INIT_MODE_WKUPCS (1 << 2)
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#define INIT_MODE_WKUPCS (1 << 2)
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#define INIT_MODE_PWRON (1 << 1)
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#define INIT_MODE_PWRON (1 << 1)
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#define INIT_MODE_SOFTCT (1 << 0)
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#define INIT_MODE_SOFTCT (1 << 0)
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/* Initialization Interrupt Enable register bits */
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/* Initialization Interrupt Enable register bits */
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#define INIT_INTEN_IEP7TX (1 << 25)
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#define INIT_INTEN_IEP7TX (1 << 25)
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#define INIT_INTEN_IEP7RX (1 << 24)
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#define INIT_INTEN_IEP7RX (1 << 24)
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#define INIT_INTEN_IEP6TX (1 << 23)
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#define INIT_INTEN_IEP6TX (1 << 23)
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#define INIT_INTEN_IEP6RX (1 << 22)
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#define INIT_INTEN_IEP6RX (1 << 22)
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#define INIT_INTEN_IEP5TX (1 << 21)
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#define INIT_INTEN_IEP5TX (1 << 21)
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#define INIT_INTEN_IEP5RX (1 << 20)
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#define INIT_INTEN_IEP5RX (1 << 20)
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#define INIT_INTEN_IEP4TX (1 << 19)
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#define INIT_INTEN_IEP4TX (1 << 19)
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#define INIT_INTEN_IEP4RX (1 << 18)
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#define INIT_INTEN_IEP4RX (1 << 18)
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#define INIT_INTEN_IEP3TX (1 << 17)
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#define INIT_INTEN_IEP3TX (1 << 17)
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#define INIT_INTEN_IEP3RX (1 << 16)
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#define INIT_INTEN_IEP3RX (1 << 16)
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#define INIT_INTEN_IEP2TX (1 << 15)
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#define INIT_INTEN_IEP2TX (1 << 15)
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#define INIT_INTEN_IEP2RX (1 << 14)
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#define INIT_INTEN_IEP2RX (1 << 14)
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#define INIT_INTEN_IEP1TX (1 << 13)
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#define INIT_INTEN_IEP1TX (1 << 13)
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#define INIT_INTEN_IEP1RX (1 << 12)
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#define INIT_INTEN_IEP1RX (1 << 12)
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#define INIT_INTEN_IEP0TX (1 << 11)
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#define INIT_INTEN_IEP0TX (1 << 11)
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#define INIT_INTEN_IEP0RX (1 << 10)
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#define INIT_INTEN_IEP0RX (1 << 10)
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#define INIT_INTEN_IEP0SETUP (1 << 8)
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#define INIT_INTEN_IEP0SETUP (1 << 8)
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#define INIT_INTEN_IEVBUS (1 << 7)
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#define INIT_INTEN_IEVBUS (1 << 7)
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#define INIT_INTEN_IEDMA (1 << 6)
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#define INIT_INTEN_IEDMA (1 << 6)
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#define INIT_INTEN_IEHS_STA (1 << 5)
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#define INIT_INTEN_IEHS_STA (1 << 5)
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#define INIT_INTEN_IERESM (1 << 4)
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#define INIT_INTEN_IERESM (1 << 4)
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#define INIT_INTEN_IESUSP (1 << 3)
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#define INIT_INTEN_IESUSP (1 << 3)
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#define INIT_INTEN_IEPSOF (1 << 2)
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#define INIT_INTEN_IEPSOF (1 << 2)
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#define INIT_INTEN_IESOF (1 << 1)
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#define INIT_INTEN_IESOF (1 << 1)
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#define INIT_INTEN_IEBRST (1 << 0)
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#define INIT_INTEN_IEBRST (1 << 0)
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/* Initialization Interrupt Configuration register bits */
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/* Initialization Interrupt Configuration register bits */
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#define INIT_INTCONF_INTLVL (1 << 1)
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#define INIT_INTCONF_INTLVL (1 << 1)
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#define INIT_INTCONF_INTPOL (1 << 0)
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#define INIT_INTCONF_INTPOL (1 << 0)
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/* Initialization Address register bits */
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/* Initialization Address register bits */
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#define INIT_ADDRESS_DEVEN (1 << 7)
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#define INIT_ADDRESS_DEVEN (1 << 7)
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/* Data Flow registers' bits */
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/* Data Flow registers' bits */
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/* Data Flow Endpoint Index register bits */
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/* Data Flow Endpoint Index register bits */
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#define DFLOW_EPINDEX_EP0SETUP (1 << 5)
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#define DFLOW_EPINDEX_EP0SETUP (1 << 5)
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/* Data Flow Control Function register bits */
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/* Data Flow Control Function register bits */
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#define DFLOW_CTRLFUN_CLBUF (1 << 4)
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#define DFLOW_CTRLFUN_CLBUF (1 << 4)
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#define DFLOW_CTRLFUN_VENDP (1 << 3)
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#define DFLOW_CTRLFUN_VENDP (1 << 3)
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#define DFLOW_CTRLFUN_DSEN (1 << 2)
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#define DFLOW_CTRLFUN_DSEN (1 << 2)
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#define DFLOW_CTRLFUN_STATUS (1 << 1)
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#define DFLOW_CTRLFUN_STATUS (1 << 1)
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#define DFLOW_CTRLFUN_STALL (1 << 0)
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#define DFLOW_CTRLFUN_STALL (1 << 0)
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/* Data Flow Endpoint Type register bits */
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/* Data Flow Endpoint Type register bits */
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#define DFLOW_EPTYPE_NOEMPKT (1 << 4)
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#define DFLOW_EPTYPE_NOEMPKT (1 << 4)
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#define DFLOW_EPTYPE_ENABLE (1 << 3)
|
#define DFLOW_EPTYPE_ENABLE (1 << 3)
|
||||||
#define DFLOW_EPTYPE_DBLBUF (1 << 2)
|
#define DFLOW_EPTYPE_DBLBUF (1 << 2)
|
||||||
|
|
||||||
/* General registers' bits */
|
/* General registers' bits */
|
||||||
|
|
||||||
/* General Test Mode register bits */
|
/* General Test Mode register bits */
|
||||||
#define GEN_TSTMOD_FORCEHS (1 << 7)
|
#define GEN_TSTMOD_FORCEHS (1 << 7)
|
||||||
#define GEN_TSTMOD_FORCEFS (1 << 4)
|
#define GEN_TSTMOD_FORCEFS (1 << 4)
|
||||||
#define GEN_TSTMOD_PRBS (1 << 3)
|
#define GEN_TSTMOD_PRBS (1 << 3)
|
||||||
#define GEN_TSTMOD_KSTATE (1 << 2)
|
#define GEN_TSTMOD_KSTATE (1 << 2)
|
||||||
#define GEN_TSTMOD_JSTATE (1 << 1)
|
#define GEN_TSTMOD_JSTATE (1 << 1)
|
||||||
#define GEN_TSTMOD_SE0_NAK (1 << 0)
|
#define GEN_TSTMOD_SE0_NAK (1 << 0)
|
||||||
|
|
||||||
/* Interrupts */
|
/* Interrupts */
|
||||||
#define INT_IEP7TX (1 << 25)
|
#define INT_IEP7TX (1 << 25)
|
||||||
#define INT_IEP7RX (1 << 24)
|
#define INT_IEP7RX (1 << 24)
|
||||||
#define INT_IEP6TX (1 << 23)
|
#define INT_IEP6TX (1 << 23)
|
||||||
#define INT_IEP6RX (1 << 22)
|
#define INT_IEP6RX (1 << 22)
|
||||||
#define INT_IEP5TX (1 << 21)
|
#define INT_IEP5TX (1 << 21)
|
||||||
#define INT_IEP5RX (1 << 20)
|
#define INT_IEP5RX (1 << 20)
|
||||||
#define INT_IEP4TX (1 << 19)
|
#define INT_IEP4TX (1 << 19)
|
||||||
#define INT_IEP4RX (1 << 18)
|
#define INT_IEP4RX (1 << 18)
|
||||||
#define INT_IEP3TX (1 << 17)
|
#define INT_IEP3TX (1 << 17)
|
||||||
#define INT_IEP3RX (1 << 16)
|
#define INT_IEP3RX (1 << 16)
|
||||||
#define INT_IEP2TX (1 << 15)
|
#define INT_IEP2TX (1 << 15)
|
||||||
#define INT_IEP2RX (1 << 14)
|
#define INT_IEP2RX (1 << 14)
|
||||||
#define INT_IEP1TX (1 << 13)
|
#define INT_IEP1TX (1 << 13)
|
||||||
#define INT_IEP1RX (1 << 12)
|
#define INT_IEP1RX (1 << 12)
|
||||||
#define INT_IEP0TX (1 << 11)
|
#define INT_IEP0TX (1 << 11)
|
||||||
#define INT_IEP0RX (1 << 10)
|
#define INT_IEP0RX (1 << 10)
|
||||||
#define INT_IEP0SETUP (1 << 8)
|
#define INT_IEP0SETUP (1 << 8)
|
||||||
#define INT_IEVBUS (1 << 7)
|
#define INT_IEVBUS (1 << 7)
|
||||||
#define INT_IEDMA (1 << 6)
|
#define INT_IEDMA (1 << 6)
|
||||||
#define INT_IEHS_STA (1 << 5)
|
#define INT_IEHS_STA (1 << 5)
|
||||||
#define INT_IERESM (1 << 4)
|
#define INT_IERESM (1 << 4)
|
||||||
#define INT_IESUSP (1 << 3)
|
#define INT_IESUSP (1 << 3)
|
||||||
#define INT_IEPSOF (1 << 2)
|
#define INT_IEPSOF (1 << 2)
|
||||||
#define INT_IESOF (1 << 1)
|
#define INT_IESOF (1 << 1)
|
||||||
#define INT_IEBRST (1 << 0)
|
#define INT_IEBRST (1 << 0)
|
||||||
|
|
||||||
#define INT_EP_MASK ( INT_IEP0RX | INT_IEP0TX | INT_IEP1RX | INT_IEP1TX | INT_IEP2RX | INT_IEP2TX | INT_IEP3RX | INT_IEP3TX | INT_IEP4RX | INT_IEP4TX | INT_IEP5RX | INT_IEP5TX | INT_IEP6RX | INT_IEP6TX | INT_IEP7RX | INT_IEP7TX )
|
#define INT_EP_MASK ( INT_IEP0RX | INT_IEP0TX | INT_IEP1RX | INT_IEP1TX | INT_IEP2RX | INT_IEP2TX | INT_IEP3RX | INT_IEP3TX | INT_IEP4RX | INT_IEP4TX | INT_IEP5RX | INT_IEP5TX | INT_IEP6RX | INT_IEP6TX | INT_IEP7RX | INT_IEP7TX )
|
||||||
|
|
||||||
#define STANDARD_INTEN ( INIT_INTEN_IEBRST | INIT_INTEN_IEHS_STA | INT_IESUSP | INT_IERESM | INIT_INTEN_IEVBUS | INIT_INTEN_IEP0SETUP | INIT_INTEN_IEP0RX | INIT_INTEN_IEP0TX )
|
#define STANDARD_INTEN ( INIT_INTEN_IEBRST | INIT_INTEN_IEHS_STA | INT_IESUSP | INT_IERESM | INIT_INTEN_IEVBUS | INIT_INTEN_IEP0SETUP | INIT_INTEN_IEP0RX | INIT_INTEN_IEP0TX )
|
||||||
#define STANDARD_INIT_MODE ( INIT_MODE_CLKAON | INIT_MODE_GLINTENA )
|
#define STANDARD_INIT_MODE ( INIT_MODE_CLKAON | INIT_MODE_GLINTENA )
|
||||||
|
|
||||||
#ifdef USE_IRAM
|
#ifdef USE_IRAM
|
||||||
#define IRAM_ATTR __attribute__ ((section(".icode")))
|
#define IRAM_ATTR __attribute__ ((section(".icode")))
|
||||||
#else
|
#else
|
||||||
#define IRAM_ATTR
|
#define IRAM_ATTR
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "usb_drv.h"
|
#include "usb_drv.h"
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,7 @@
|
||||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
* \/ \/ \/ \/ \/
|
* \/ \/ \/ \/ \/
|
||||||
* $Id: $
|
* $Id$
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 by Karl Kurbjun
|
* Copyright (C) 2009 by Karl Kurbjun
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,7 @@
|
||||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
* \/ \/ \/ \/ \/
|
* \/ \/ \/ \/ \/
|
||||||
* $Id: $
|
* $Id$
|
||||||
*
|
*
|
||||||
* Copyright (C) 2002 by Alan Korr
|
* Copyright (C) 2002 by Alan Korr
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,7 @@
|
||||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
* \/ \/ \/ \/ \/
|
* \/ \/ \/ \/ \/
|
||||||
* $Id: S5L8700X.h 2008-03-27 Marcoen Hirschberg, Bart van Adrichem $
|
* $Id$
|
||||||
*
|
*
|
||||||
* Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
|
* Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,7 @@
|
||||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
* \/ \/ \/ \/ \/
|
* \/ \/ \/ \/ \/
|
||||||
* $Id: $
|
* $Id$
|
||||||
*
|
*
|
||||||
* Copyright (C) 2007 by Catalin Patulea
|
* Copyright (C) 2007 by Catalin Patulea
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,7 @@
|
||||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
* \/ \/ \/ \/ \/
|
* \/ \/ \/ \/ \/
|
||||||
* $Id: $
|
* $Id$
|
||||||
*
|
*
|
||||||
* Copyright (C) 2007 by Jonathan Gordon
|
* Copyright (C) 2007 by Jonathan Gordon
|
||||||
*
|
*
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue