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hwstub/atj213x: add clock setup to crt0.S

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Change-Id: I3b6e1b8ee1fa76396f7abe7df69af26e9599cfe9
Reviewed-on: http://gerrit.rockbox.org/1055
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
Tested: Marcin Bukat <marcin.bukat@gmail.com>
This commit is contained in:
Marcin Bukat 2014-11-28 12:15:57 +01:00
parent 5e1381be87
commit 0cd9e4e6bc
1 changed files with 29 additions and 1 deletions
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30
utils/hwstub/stub/atj213x/crt0.S
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@ -5,6 +5,7 @@
.set mips32r2
.set noreorder
.set noat
.section .init.text,"ax",%progbits
@ -18,6 +19,30 @@ load_addr:
# account for branch delay slot
# and very first 'di' instruction
core_clk_setup:
la t0, 0xb0010000 # CMU base
li t1, 0x440 # HOSC enable, bypass
sw t1, 0(t0) # CMU_COREPLL
li t1, 0x350 # CORECLKS 24M, CCLKDIV = 1, SCLKDIV = 2,
# PCLKDIV = 4
sw t1, 0x0c(t0) # CMU_BUSCLK
li t1, 0xc6 # HOSC enable, PLL enable, 6*6M = 36M
sw t1, 0(t0) # CMU_COREPLL
nop
nop
nop
nop
nop
nop
nop
nop # arbitrary 300ns delay as there is no
# PLL lock feedback
li t1, 0x390 # CORECLKS COREPLL, CCLKDIV = 1, SCLKDIV = 2,
# PCLKDIV = 4
sw t1, 0x0c(t0) # CMU_BUSCLK
cache_setup:
la t0, 0x80000000 # an idx op should use an unmappable address
ori t1, t0, 0x4000 # 16kB cache
mtc0 zero, C0_TAGLO
@ -53,11 +78,13 @@ reloc_loop:
# icache invalidate
addiu t0, t0, 16 # inc dst addr
blt t0, t1, reloc_loop
slt t2, t0, t1
bnez t2, reloc_loop
addiu v0, v0, 16 # inc src addr
entry_point_jump:
la t0, entry_point
sync
jr.hb t0
nop
@ -200,6 +227,7 @@ restore:
addiu sp, sp, 84
move sp, k1
eret
nop
.set reorder
.set at