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mips: Heavily rework DMA & caching code

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Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.

Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
This commit is contained in:
Solomon Peachy 2020-08-28 21:45:58 -04:00
parent 1ae8213a64
commit 0cb162a76b
16 changed files with 188 additions and 129 deletions
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2
firmware/rolo.c
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@ -201,7 +201,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
: : "r"(dest)
);
#elif defined(CPU_MIPS)
__dcache_writeback_all();
commit_discard_idcache();
asm volatile(
"jr %0 \n"
: : "r"(dest)