devs/foxbox
1
0
Fork 0
forked from len0rd/rockbox
Code Pull requests Activity

Sansa AMS: Use a valid PLL setting (248MHz aka maximum fclk)

Browse source 
Fix lcd drivers which stopped working after changing the PLL.
Move set_cpu_frequency() to a place where it is actually used.
Remove enable_irq() call already done by the bootloader

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19276 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2008-11-30 16:36:32 +00:00
parent f235f1d4c0
commit 0b6d65b09e
5 changed files with 12 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

2
firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
View file

@ -94,7 +94,7 @@ static void lcd_delay(int x)
/* DBOP initialisation, do what OF does */ /* DBOP initialisation, do what OF does */
static void ams3525_dbop_init(void) static void ams3525_dbop_init(void)
{ {
CGU_DBOP = (1<<3) | (4-1); CGU_DBOP = (1<<3) | (3-1);
DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e; DBOP_TIMPOL_23 = 0xe167006e;

3
firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c
View file

@ -49,8 +49,7 @@ static void lcd_delay(int x)
static void as3525_dbop_init(void) static void as3525_dbop_init(void)
{ {
CGU_DBOP = (1<<3) | (4-1); CGU_DBOP = (1<<3);
DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e; DBOP_TIMPOL_23 = 0xe167006e;
DBOP_CTRL = 0x41008; DBOP_CTRL = 0x41008;

16
firmware/target/arm/as3525/system-as3525.c
View file

@ -215,15 +215,10 @@ void system_init(void)
"mcr p15, 0, r0, c1, c0 \n" "mcr p15, 0, r0, c1, c0 \n"
: : : "r0" ); : : : "r0" );
CGU_PLLA = 0x4330; /* PLLA 384 MHz */ CGU_PLLA = 0x261F; /* PLLA 248 MHz */
while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
CGU_PROC = (3<<2)|0x01; /* fclk = PLLA*5/8 = 240 MHz */ CGU_PROC = 1; /* fclk = PLLA = 248 MHz */
#ifndef BOOTLOADER
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
set_cpu_frequency(CPUFREQ_DEFAULT);
#endif
#endif
asm volatile( asm volatile(
"mov r0, #0 \n" "mov r0, #0 \n"
@ -243,16 +238,17 @@ void system_init(void)
VIC_INT_ENABLE = 0; /* disable all interrupt lines */ VIC_INT_ENABLE = 0; /* disable all interrupt lines */
CGU_PERI |= CGU_VIC_CLOCK_ENABLE; CGU_PERI |= CGU_VIC_CLOCK_ENABLE;
VIC_INT_SELECT = 0; /* only IRQ, no FIQ */ VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
enable_irq();
#else #else
/* Disable fast hardware power-off, to use power button normally /* Disable fast hardware power-off, to use power button normally
* We don't need the power button in the bootloader. */ * We don't need the power button in the bootloader. */
ascodec_init(); ascodec_init();
ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2)); ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2));
#endif /* BOOTLOADER */ #endif /* BOOTLOADER */
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
set_cpu_frequency(CPUFREQ_DEFAULT);
#endif
dma_init(); dma_init();
} }

6
firmware/target/arm/as3525/system-target.h
View file

@ -23,8 +23,8 @@
#include "system-arm.h" #include "system-arm.h"
#define CPUFREQ_MAX 240000000 #define CPUFREQ_MAX 248000000
#define CPUFREQ_DEFAULT 24000000 #define CPUFREQ_DEFAULT 24800000
#define CPUFREQ_NORMAL 30000000 #define CPUFREQ_NORMAL 31000000
#endif /* SYSTEM_TARGET_H */ #endif /* SYSTEM_TARGET_H */

4
firmware/target/arm/lcd-ssd1815.c
View file

@ -102,9 +102,7 @@ void lcd_write_data(const fb_data* p_bytes, int count)
static inline void ams3525_dbop_init(void) static inline void ams3525_dbop_init(void)
{ {
int clkdiv = 4 - 1; CGU_DBOP |= (1<<3) /* clk enable */ | (3 - 1) /* clkdiv: 3 bits */ ;
CGU_DBOP |= (1<<3) /* clk enable */ | clkdiv /* clkdiv: 3 bits */ ;
GPIOB_AFSEL = 0x0f; /* DBOP on pin 3:0 */ GPIOB_AFSEL = 0x0f; /* DBOP on pin 3:0 */
GPIOC_AFSEL = 0xff; /* DBOP on pins 7:0 */ GPIOC_AFSEL = 0xff; /* DBOP on pins 7:0 */