forked from len0rd/rockbox
Serial driver for imx31. Perhaps not 100% but maybe 80-90% (future developments will tell). Factor-out the mc13783 stuff and make that driver a layer above the SPI. TODO: start processing PMIC interrupts. Start a clkctl API for imx31 (we'll see if this sticks around but it seems reasonable here). Misc. stuff for convenience/neatness.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17070 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
f46a7533a4
commit
0b1d7e76d7
13 changed files with 858 additions and 87 deletions
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@ -516,32 +516,41 @@
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#define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
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/* CSPI */
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#define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
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#define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
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#define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
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#define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
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#define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
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#define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
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#define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
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#define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
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#define CSPI_RXDATA_I 0x00 /* Offset - 0x00 */
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#define CSPI_TXDATA_I 0x01 /* Offset - 0x04 */
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#define CSPI_CONREG_I 0x02 /* Offset - 0x08 */
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#define CSPI_INTREG_I 0x03 /* Offset - 0x0C */
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#define CSPI_DMAREG_I 0x04 /* Offset - 0x10 */
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#define CSPI_STATREG_I 0x05 /* Offset - 0x14 */
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#define CSPI_PERIODREG_I 0x06 /* Offset - 0x18 */
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#define CSPI_TESTREG_I 0x70 /* Offset - 0x1C0 */
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#define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
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#define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
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#define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
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#define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
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#define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
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#define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
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#define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
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#define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
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#define CSPI_RXDATA1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_RXDATA_I])
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#define CSPI_TXDATA1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TXDATA_I])
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#define CSPI_CONREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_CONREG_I])
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#define CSPI_INTREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_INTREG_I])
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#define CSPI_DMAREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_DMAREG_I])
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#define CSPI_STATREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_STATREG_I])
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#define CSPI_PERIODREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_PERIODREG_I])
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#define CSPI_TESTREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TESTREG_I])
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#define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00))
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#define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04))
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#define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08))
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#define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C))
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#define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10))
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#define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14))
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#define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18))
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#define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0))
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#define CSPI_RXDATA2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_RXDATA_I])
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#define CSPI_TXDATA2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TXDATA_I])
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#define CSPI_CONREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_CONREG_I])
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#define CSPI_INTREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_INTREG_I])
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#define CSPI_DMAREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_DMAREG_I])
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#define CSPI_STATREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_STATREG_I])
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#define CSPI_PERIODREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_PERIODREG_I])
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#define CSPI_TESTREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TESTREG_I])
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#define CSPI_RXDATA3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_RXDATA_I])
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#define CSPI_TXDATA3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TXDATA_I])
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#define CSPI_CONREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_CONREG_I])
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#define CSPI_INTREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_INTREG_I])
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#define CSPI_DMAREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_DMAREG_I])
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#define CSPI_STATREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_STATREG_I])
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#define CSPI_PERIODREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_PERIODREG_I])
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#define CSPI_TESTREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TESTREG_I])
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/* CSPI CONREG flags/fields */
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#define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24)
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@ -563,6 +572,7 @@
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#define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16)
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#define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16)
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#define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16)
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#define CSPI_BITCOUNT(n) ((n) << 8)
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#define CSPI_CONREG_SSPOL (1 << 7)
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#define CSPI_CONREG_SSCTL (1 << 6)
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#define CSPI_CONREG_PHA (1 << 6)
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@ -581,7 +591,7 @@
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#define CSPI_INTREG_RREN (1 << 3)
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#define CSPI_INTREG_TFEN (1 << 2)
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#define CSPI_INTREG_THEN (1 << 1)
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#define CSPI_INTREF_TEEN (1 << 0)
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#define CSPI_INTREG_TEEN (1 << 0)
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/* CSPI DMAREG flags */
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#define CSPI_DMAREG_RFDEN (1 << 5)
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@ -764,12 +774,6 @@
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#define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
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#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
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#define CG_OFF 0x0 /* Always off */
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#define CG_ON_RUN 0x1 /* On in run mode, off in wait and doze */
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#define CG_ON_RUN_WAIT 0x2 /* On in run and wait modes, off in doze */
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#define CG_ON_ALL 0x3 /* Always on */
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#define CG_MASK 0x3 /* bitmask */
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#define CGR0_SD_MMC1(cg) ((cg) << 0*2)
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#define CGR0_SD_MMC2(cg) ((cg) << 1*2)
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#define CGR0_GPT(cg) ((cg) << 2*2)
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@ -812,6 +816,39 @@
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#define CGR2_RTIC(cg) ((cg) << 5*2)
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#define CGR2_FIR(cg) ((cg) << 6*2)
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#define WIM_GPIO3 (1 << 0)
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#define WIM_GPIO2 (1 << 1)
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#define WIM_GPIO1 (1 << 2)
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#define WIM_PCMCIA (1 << 3)
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#define WIM_WDT (1 << 4)
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#define WIM_USB_OTG (1 << 5)
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#define WIM_IPI_INT_UH2 (1 << 6)
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#define WIM_IPI_INT_UH1 (1 << 7)
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#define WIM_IPI_INT_UART5_ANDED (1 << 8)
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#define WIM_IPI_INT_UART4_ANDED (1 << 9)
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#define WIM_IPI_INT_UART3_ANDED (1 << 10)
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#define WIM_IPI_INT_UART2_ANDED (1 << 11)
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#define WIM_IPI_INT_UART1_ANDED (1 << 12)
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#define WIM_IPI_INT_SIM_DATA_IRQ (1 << 13)
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#define WIM_IPI_INT_SDHC2 (1 << 14)
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#define WIM_IPI_INT_SDHC1 (1 << 15)
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#define WIM_IPI_INT_RTC (1 << 16)
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#define WIM_IPI_INT_PWM (1 << 17)
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#define WIM_IPI_INT_KPP (1 << 18)
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#define WIM_IPI_INT_IIM (1 << 19)
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#define WIM_IPI_INT_GPT (1 << 20)
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#define WIM_IPI_INT_FIR (1 << 21)
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#define WIM_IPI_INT_EPIT2 (1 << 22)
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#define WIM_IPI_INT_EPIT1 (1 << 23)
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#define WIM_IPI_INT_CSPI2 (1 << 24)
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#define WIM_IPI_INT_CSPI1 (1 << 25)
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#define WIM_IPI_INT_POWER_FAIL (1 << 26)
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#define WIM_IPI_INT_CSPI3 (1 << 27)
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#define WIM_RESERVED28 (1 << 28)
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#define WIM_RESERVED29 (1 << 29)
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#define WIM_RESERVED30 (1 << 30)
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#define WIM_RESERVED31 (1 << 31)
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/* WEIM - CS0 */
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#define CSCRU 0x00
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#define CSCRL 0x04
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