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jz4760: Move 11/22/44/88KHz back onto the PLL

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PLL1 clock for those frequencies has been dropped from 508 to 169.5 MHz,
so it's still a respectable reduction.

(I'm not sure how/why it ever worked with the XTAL source, but it did,
 and was off by an audible amount)

Change-Id: I614d87e7dfdfe9210702b9c646d3863c06d6780b
This commit is contained in:
Solomon Peachy 2020-08-08 22:25:04 -04:00
parent be2c8734cb
commit 08c4b708ae
1 changed files with 16 additions and 8 deletions
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24
firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
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@ -219,8 +219,10 @@ void audiohw_set_frequency(int fsel)
func_mode = 0;
break;
case HW_FREQ_11: // 0.7056 MHz
pll1_speed = 0;
mclk_div = 272;
pll1_speed = 508000000 / 3;
mclk_div = 180 / 3;
// pll1_speed = 0;
// mclk_div = 272;
bclk_div = 4;
func_mode = 0;
break;
@ -237,8 +239,10 @@ void audiohw_set_frequency(int fsel)
func_mode = 0;
break;
case HW_FREQ_22: // 1.4112 MHz
pll1_speed = 0;
mclk_div = 136;
pll1_speed = 508000000 / 3;
mclk_div = 90 / 3;
// pll1_speed = 0;
// mclk_div = 136;
bclk_div = 4;
func_mode = 0;
break;
@ -256,8 +260,10 @@ void audiohw_set_frequency(int fsel)
func_mode = 0;
break;
case HW_FREQ_44: // 2.8224 MHz
pll1_speed = 0;
mclk_div = 68;
pll1_speed = 508000000 / 3;
mclk_div = 45 / 3;
// pll1_speed = 0;
// mclk_div = 68;
bclk_div = 4;
dem = CS4398_DEM_44100;
func_mode = 0;
@ -276,8 +282,10 @@ void audiohw_set_frequency(int fsel)
func_mode = 1;
break;
case HW_FREQ_88: // 5.6448 MHz
pll1_speed = 0;
mclk_div = 68;
pll1_speed = 508000000 / 3;
mclk_div = 45 / 3;
// pll1_speed = 0;
// mclk_div = 68;
bclk_div = 2;
func_mode = 1;
break;