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Slightly better instruction order, added comment.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16833 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2008-03-26 23:45:55 +00:00
parent 91a564e4b9
commit 06ec18d93f
2 changed files with 11 additions and 7 deletions
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8
firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S
View file

@ -32,6 +32,7 @@
/* Output 8 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
* Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@ -63,8 +64,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
bra.w .wr_bit7
@ -72,6 +73,7 @@
/* Output 16 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
* Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@ -102,8 +104,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
nop
@ -113,8 +115,8 @@
eor.l %d6, %d0
1:
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
move.l %d0, %d1
move.l %d0, (%a0)
move.l %d0, %d1
eor.l %d7, %d1
.endm
bit_out

8
firmware/target/coldfire/iaudio/m3/lcd-as-m3.S
View file

@ -32,6 +32,7 @@
/* Output 8 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
* Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@ -63,8 +64,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
bra.w .wr_bit7
@ -72,6 +73,7 @@
/* Output 16 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
* Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@ -102,8 +104,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
move.l %d0, %d1
eor.l %d7, %d1
nop
@ -113,8 +115,8 @@
eor.l %d6, %d0
1:
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
move.l %d0, %d1
move.l %d0, (%a0)
move.l %d0, %d1
eor.l %d7, %d1
.endm
bit_out