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imx233/fuze+: prepare target to enable MMU

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30199 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Amaury Pouly 2011-07-23 11:45:18 +00:00
parent 3f8bf5e041
commit 06c94740e5
4 changed files with 35 additions and 16 deletions
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14
firmware/export/imx233.h
View file

@ -24,12 +24,14 @@
#define IRAM_ORIG 0
#define IRAM_SIZE 0x8000
#define DRAM_ORIG 0x40000000
#define DRAM_SIZE 0x20000000
#define DRAM_SIZE (MEMORYSIZE * 0x100000)
#define TTB_BASE_ADDR (DRAM_ORIG + (MEMORYSIZE*0x100000) - TTB_SIZE)
#define TTB_SIZE (0x4000)
#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
#define FRAME_SIZE (240*320*2)
#define TTB_BASE_ADDR (IRAM_ORIG + IRAM_SIZE - TTB_SIZE)
#define TTB_SIZE 0x4000
#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
#define FRAME_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8)
#define LCD_FRAME_ADDR (DRAM_ORIG + DRAM_SIZE - FRAME_SIZE)
#define FRAME ((unsigned short *)LCD_FRAME_ADDR)
/* USBOTG */
#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
@ -48,5 +50,7 @@
#define __BLOCK_SFTRST (1 << 31)
#define __BLOCK_CLKGATE (1 << 30)
#define CACHEALIGN_BITS 4
#endif /* __IMX233_H__ */

6
firmware/target/arm/imx233/boot.lds
View file

@ -8,8 +8,8 @@ STARTUP(target/arm/imx233/crt0.o)
MEMORY
{
IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE
DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE - TTB_SIZE
IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE - TTB_SIZE
DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE - FRAME_SIZE
}
SECTIONS
@ -30,7 +30,7 @@ SECTIONS
{
_iramstart = .; // always 0
*(.vectors)
KEEP(*(.vectors));// otherwise there are no reference to it and the linker strip it
KEEP(*(.vectors));// otherwise there are no references to it and the linker strip it
*(.icode)
*(.irodata)
*(.idata)

27
firmware/target/arm/imx233/system-imx233.c
View file

@ -141,6 +141,25 @@ void imx233_softirq(int src, bool enable)
__REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__SOFTIRQ;
}
static void set_page_tables(void)
{
/* map every memory region to itself */
map_section(0, 0, 0x1000, CACHE_NONE);
/* map RAM and enable caching for it */
map_section(DRAM_ORIG, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
/* enable buffered writing for the framebuffer */
map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
}
void memory_init(void)
{
ttb_init();
set_page_tables();
enable_mmu();
}
void system_init(void)
{
/* disable all interrupts */
@ -158,14 +177,6 @@ void system_init(void)
imx233_timrot_init();
imx233_dma_init();
imx233_ssp_init();
imx233_i2c_init();
}
void power_off(void)
{
/* power down */
HW_POWER_RESET = HW_POWER_RESET__UNLOCK | HW_POWER_RESET__PWD;
while(1);
}
bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)

4
firmware/target/arm/mmu-arm.S
View file

@ -44,6 +44,10 @@
/* MMU not present */
#define CACHE_SIZE 4
#elif CONFIG_CPU == IMX233
#define USE_MMU
#define CACHE_SIZE 16
#else
#error Cache settings unknown for this CPU !