forked from len0rd/rockbox
Fixed formatting (uniform indentation of 4 spaces, removed tab chars). Some slight optimisations.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6822 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
055303ad7d
commit
06109b0202
1 changed files with 367 additions and 366 deletions
733
firmware/crt0.S
733
firmware/crt0.S
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@ -16,460 +16,461 @@
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#include "config.h"
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#include "cpu.h"
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.section .init.text
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.global start
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.section .init.text
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.global start
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start:
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#if CONFIG_CPU == TCC730
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;; disable all interrupts
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clrsr fe
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clrsr ie
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clrsr te
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ld a14, #0x3F0000
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/* Platform: Gmini 120/SP */
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;; disable all interrupts
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clrsr fe
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clrsr ie
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clrsr te
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ld a14, #0x3F0000
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ld r5, 0xA5
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ldb @[a14 + 6], r5 ; disable watchdog
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ld a11, #(_datacopy) ; where the data section is in the flash
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ld a8, #(_datastart) ; destination
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ld r5, 0xA5
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ldb @[a14 + 6], r5 ; disable watchdog
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;; copy data section from flash to ram.
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ld a9, #_datasize
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ld r6, e9
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cmp eq, r6, #0
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brf .data_copy_loop
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cmp eq, r9, #0
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brt .data_copy_end
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.data_copy_loop:
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ldc r2, @a11
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ldw @[a8 + 0], r2
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add a11, #0x2
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add a8, #0x2
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sub r9, #0x2
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sbc r6, #0
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cmp ugt, r6, #0
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brt .data_copy_loop
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cmp ugt, r9, #0
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brt .data_copy_loop
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ld a11, #(_datacopy) ; where the data section is in the flash
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ld a8, #(_datastart) ; destination
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;; copy data section from flash to ram.
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ld a9, #_datasize
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ld r6, e9
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cmp eq, r6, #0
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brf .data_copy_loop
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cmp eq, r9, #0
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brt .data_copy_end
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.data_copy_loop:
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ldc r2, @a11
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ldw @[a8 + 0], r2
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add a11, #0x2
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add a8, #0x2
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sub r9, #0x2
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sbc r6, #0
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cmp ugt, r6, #0
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brt .data_copy_loop
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cmp ugt, r9, #0
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brt .data_copy_loop
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.data_copy_end:
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;; zero out bss
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ld r2, #0
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ld a8, #(_bssstart) ; destination
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ld a9, #_bsssize
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ld r6, e9
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;; zero out bss
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ld r2, #0
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ld a8, #(_bssstart) ; destination
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ld a9, #_bsssize
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ld r6, e9
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cmp eq, r6, #0
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brf .bss_init_loop
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cmp eq, r9, #0
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brt .bss_init_end
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.bss_init_loop:
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ldw @[a8 + 0], r2
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add a8, #0x2
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sub r9, #0x2
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sbc r6, #0
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cmp ugt, r6, #0
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brt .bss_init_loop
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cmp ugt, r9, #0
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brt .bss_init_loop
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cmp eq, r6, #0
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brf .bss_init_loop
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cmp eq, r9, #0
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brt .bss_init_end
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.bss_init_loop:
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ldw @[a8 + 0], r2
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add a8, #0x2
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sub r9, #0x2
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sbc r6, #0
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cmp ugt, r6, #0
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brt .bss_init_loop
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cmp ugt, r9, #0
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brt .bss_init_loop
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.bss_init_end:
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;; set stack pointer
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ld a15, _stackend
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;; set stack pointer
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ld a15, _stackend
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;; go!
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jsr _main
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;; soft reset
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ld a10, #0
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ldc r10, @a10
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jmp a10
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;; go!
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jsr _main
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.section .vectors, "ax"
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;; soft reset
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ld a10, #0
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ldc r10, @a10
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jmp a10
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.section .vectors, "ax"
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irq_handler:
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push r0, r1
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push r2, r3
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push r4, r5
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push r6, r7
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push a8, a9
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push a10, a11
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push a12, a13
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push a14
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ld a13, #0x3f0000
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ldb r0, @[a13 + 0x26]
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add r0, r0
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ld a10, #_interrupt_vector
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ldw a13, @[a10 + r0]
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jsr a13
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pop a14
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pop a13, a12
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pop a11, a10
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pop a9, a8
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pop r7, r6
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pop r5, r4
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pop r3, r2
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pop r1, r0
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ret_irq
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push r0, r1
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push r2, r3
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push r4, r5
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push r6, r7
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push a8, a9
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push a10, a11
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push a12, a13
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push a14
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ld a13, #0x3f0000
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ldb r0, @[a13 + 0x26]
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add r0, r0
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ld a10, #_interrupt_vector
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ldw a13, @[a10 + r0]
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jsr a13
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pop a14
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pop a13, a12
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pop a11, a10
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pop a9, a8
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pop r7, r6
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pop r5, r4
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pop r3, r2
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pop r1, r0
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ret_irq
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#elif defined(IRIVER_H100)
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/* Platform: iRiver H120/H140 */
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move.w #0x2700,%sr
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/* Platform: iRiver H120/H140 */
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move.w #0x2700,%sr
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move.l #vectors,%d0
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movec.l %d0,%vbr
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move.l #vectors,%d0
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movec.l %d0,%vbr
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move.l #MBAR+1,%d0
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movec.l %d0,%mbar
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move.l #MBAR+1,%d0
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movec.l %d0,%mbar
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move.l #MBAR2+1,%d0
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movec.l %d0,%mbar2
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move.l #MBAR2+1,%d0
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movec.l %d0,%mbar2
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lea MBAR,%a0
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lea MBAR2,%a1
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lea MBAR,%a0
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lea MBAR2,%a1
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/* 64K DMA-capable SRAM at 0x10000000
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DMA is enabled and has priority in both banks
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10000e01,%d0
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movec.l %d0,%rambar1
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/* 64K DMA-capable SRAM at 0x10000000
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DMA is enabled and has priority in both banks
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10000e01,%d0
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movec.l %d0,%rambar1
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/* 32K Non-DMA SRAM at 0x10010000
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10010001,%d0
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movec.l %d0,%rambar0
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/* 32K Non-DMA SRAM at 0x10010000
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10010001,%d0
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movec.l %d0,%rambar0
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/* Chip select 0 - Flash ROM */
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move.l #0x00000000,%d0 /* CSAR0 - Base = 0x00000000 */
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move.l %d0,(0x080,%a0)
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move.l #0x001f0101,%d0 /* CSMR0 - 2M, All access, write protect */
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move.l %d0,(0x084,%a0)
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move.l #0x00000d80,%d0 /* CSCR0 - 3 wait states, 16 bits, no bursts */
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move.l %d0,(0x088,%a0)
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/* Chip select 0 - Flash ROM */
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moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */
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move.l %d0,(0x080,%a0)
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move.l #0x001f0101,%d0 /* CSMR0 - 2M, All access, write protect */
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move.l %d0,(0x084,%a0)
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move.l #0x00000d80,%d0 /* CSCR0 - 3 wait states, 16 bits, no bursts */
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move.l %d0,(0x088,%a0)
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/* Chip select 1 - LCD controller */
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move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
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move.l %d0,(0x08c,%a0)
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move.l #0x00000075,%d0 /* CSMR1 - 64K, Only data access */
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move.l %d0,(0x090,%a0)
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move.l #0x00000180,%d0 /* CSCR1 - 0 wait states, 16 bits, no bursts */
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move.l %d0,(0x094,%a0)
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/* Chip select 1 - LCD controller */
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move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
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move.l %d0,(0x08c,%a0)
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moveq.l #0x75,%d0 /* CSMR1 - 64K, Only data access */
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move.l %d0,(0x090,%a0)
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move.l #0x00000180,%d0 /* CSCR1 - 0 wait states, 16 bits, no bursts */
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move.l %d0,(0x094,%a0)
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/* Chip select 2 - ATA controller */
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move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
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move.l %d0,(0x098,%a0)
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move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */
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move.l %d0,(0x09c,%a0)
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move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states.
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We have to be careful with the access times,
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since IORDY isn't connected to the HDD. */
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/* Chip select 2 - ATA controller */
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move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
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move.l %d0,(0x098,%a0)
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move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */
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move.l %d0,(0x09c,%a0)
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move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states.
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We have to be careful with the access times,
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since IORDY isn't connected to the HDD. */
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#ifdef BOOTLOADER
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/* The cookie is not reset. This must mean that the boot loader
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has crashed. Let's start the original firmware immediately. */
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lea 0x10017ffc,%a2
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move.l (%a2),%d0
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move.l #0xc0015a17,%d1
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cmp.l %d0,%d1
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bne .nocookie
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/* Clear the cookie again */
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move.l #0,(%a2)
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jmp 8
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/* The cookie is not reset. This must mean that the boot loader
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has crashed. Let's start the original firmware immediately. */
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lea 0x10017ffc,%a2
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move.l (%a2),%d0
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move.l #0xc0015a17,%d1
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cmp.l %d0,%d1
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bne .nocookie
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/* Clear the cookie again */
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clr.l (%a2)
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jmp 8
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.nocookie:
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/* Set the cookie */
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move.l %d1,(%a2)
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/* Set the cookie */
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move.l %d1,(%a2)
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/* Set up the DRAM controller. The refresh is based on the 11.2896MHz
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clock (5.6448MHz bus frequency). We haven't yet started the PLL */
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move.w #0x8001,%d0
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move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */
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/* Set up the DRAM controller. The refresh is based on the 11.2896MHz
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clock (5.6448MHz bus frequency). We haven't yet started the PLL */
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move.w #0x8001,%d0
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move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */
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/* Note: we place the SDRAM on an 0x1000000 (16M) offset because
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the 5249 BGA chip has a fault which disables the use of A24. The
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suggested workaround by FreeScale is to offset the base address by
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half the DRAM size and increase the mask to the double.
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In our case this means that we set the base address 16M ahead and
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use a 64M mask.
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*/
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move.l #0x31002520,%d0
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move.l %d0,(0x108,%a0) /* DACR0 - Base 0x31000000, Banks on 23 and up,
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CAS latency 1, No refresh yet */
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move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */
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move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
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/* Note: we place the SDRAM on an 0x1000000 (16M) offset because
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the 5249 BGA chip has a fault which disables the use of A24. The
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suggested workaround by FreeScale is to offset the base address by
|
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half the DRAM size and increase the mask to the double.
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In our case this means that we set the base address 16M ahead and
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use a 64M mask.
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*/
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move.l #0x31002520,%d0
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move.l %d0,(0x108,%a0) /* DACR0 - Base 0x31000000, Banks on 23 and up,
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CAS latency 1, No refresh yet */
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move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */
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move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
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/* Precharge */
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move.l #0x31002528,%d0
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move.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a
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Precharge command */
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move.l #0xabcd1234,%d0
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move.l %d0,0x31000000 /* Issue precharge command */
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/* Precharge */
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move.l #0x31002528,%d0
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move.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a
|
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Precharge command */
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move.l #0xabcd1234,%d0
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move.l %d0,0x31000000 /* Issue precharge command */
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/* Let it refresh */
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move.l #1000,%d0
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/* Let it refresh */
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move.l #1000,%d0
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.delayloop:
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subq.l #1,%d0
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bne .delayloop
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subq.l #1,%d0
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bne .delayloop
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/* Refresh */
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move.l #0x3100a520,%d0
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move.l %d0,(0x108,%a0) /* Enable refresh */
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/* Refresh */
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move.l #0x3100a520,%d0
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move.l %d0,(0x108,%a0) /* Enable refresh */
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/* Mode Register init */
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move.l #0x3100a560,%d0 /* DACR0[IMRS] = 1, next access will set the
|
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Mode Register */
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move.l %d0,(0x108,%a0)
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/* Mode Register init */
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move.l #0x3100a560,%d0 /* DACR0[IMRS] = 1, next access will set the
|
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Mode Register */
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move.l %d0,(0x108,%a0)
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move.l #0xabcd1234,%d0
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move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */
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move.l #0xabcd1234,%d0
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move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */
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move.l #0x3100a520,%d0 /* Back to normal, the DRAM is now ready */
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move.l %d0,(0x108,%a0)
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move.l #0x3100a520,%d0 /* Back to normal, the DRAM is now ready */
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move.l %d0,(0x108,%a0)
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#endif
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/* Invalicate cache */
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move.l #0x01000000,%d0
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movec.l %d0,%cacr
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/* Invalicate cache */
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move.l #0x01000000,%d0
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movec.l %d0,%cacr
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/* Enable cache, default=non-cacheable,no buffered writes */
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move.l #0x80000000,%d0
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movec.l %d0,%cacr
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/* Enable cache, default=non-cacheable,no buffered writes */
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move.l #0x80000000,%d0
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movec.l %d0,%cacr
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||||
/* Cache enabled in SDRAM only, buffered writes enabled */
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move.l #0x3103c020,%d0
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movec.l %d0,%acr0
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move.l #0,%d0
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movec.l %d0,%acr1
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#ifndef BOOTLOADER
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||||
lea _iramcopy,%a2
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lea _iramstart,%a3
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||||
lea _iramend,%a4
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||||
/* Cache enabled in SDRAM only, buffered writes enabled */
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||||
move.l #0x3103c020,%d0
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||||
movec.l %d0,%acr0
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||||
moveq.l #0,%d0
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||||
movec.l %d0,%acr1
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||||
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#ifndef BOOTLOADER
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||||
lea _iramcopy,%a2
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||||
lea _iramstart,%a3
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||||
lea _iramend,%a4
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||||
.iramloop:
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||||
cmp.l %a3,%a4
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beq .iramloopend
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||||
move.w (%a2)+,(%a3)+
|
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bra .iramloop
|
||||
cmp.l %a3,%a4
|
||||
beq .iramloopend
|
||||
move.w (%a2)+,(%a3)+
|
||||
bra .iramloop
|
||||
.iramloopend:
|
||||
#endif
|
||||
|
||||
lea _edata,%a2
|
||||
lea _end,%a4
|
||||
clr.l %d0
|
||||
|
||||
lea _edata,%a2
|
||||
lea _end,%a4
|
||||
clr.l %d0
|
||||
.edataloop:
|
||||
cmp.l %a2,%a4
|
||||
beq .edataloopend
|
||||
move.w %d0,(%a2)+
|
||||
bra .edataloop
|
||||
cmp.l %a2,%a4
|
||||
beq .edataloopend
|
||||
move.w %d0,(%a2)+
|
||||
bra .edataloop
|
||||
.edataloopend:
|
||||
|
||||
lea _datacopy,%a2
|
||||
lea _datastart,%a3
|
||||
lea _dataend,%a4
|
||||
lea _datacopy,%a2
|
||||
lea _datastart,%a3
|
||||
lea _dataend,%a4
|
||||
.dataloop:
|
||||
cmp.l %a3,%a4
|
||||
beq .dataloopend
|
||||
move.w (%a2)+,(%a3)+
|
||||
bra .dataloop
|
||||
cmp.l %a3,%a4
|
||||
beq .dataloopend
|
||||
move.w (%a2)+,(%a3)+
|
||||
bra .dataloop
|
||||
.dataloopend:
|
||||
|
||||
/* Munge the main stack */
|
||||
lea stackbegin,%a2
|
||||
lea stackend,%a4
|
||||
move.l #0xdeadbeef,%d0
|
||||
/* Munge the main stack */
|
||||
lea stackbegin,%a2
|
||||
lea stackend,%a4
|
||||
move.l #0xdeadbeef,%d0
|
||||
.mungeloop:
|
||||
cmp.l %a2,%a4
|
||||
beq .mungeloopend
|
||||
move.l %d0,(%a2)+
|
||||
bra .mungeloop
|
||||
cmp.l %a2,%a4
|
||||
beq .mungeloopend
|
||||
move.l %d0,(%a2)+
|
||||
bra .mungeloop
|
||||
.mungeloopend:
|
||||
|
||||
lea stackend,%sp
|
||||
jsr main
|
||||
lea stackend,%sp
|
||||
jsr main
|
||||
.hoo:
|
||||
bra .hoo
|
||||
bra .hoo
|
||||
|
||||
.section .resetvectors
|
||||
.section .resetvectors
|
||||
vectors:
|
||||
.long stackend
|
||||
.long start
|
||||
.long stackend
|
||||
.long start
|
||||
#elif defined(IRIVER_H300)
|
||||
/* Platform: iRiver H320/H340 */
|
||||
/* Platform: iRiver H320/H340 */
|
||||
|
||||
/* Fill in code here */
|
||||
/* Fill in code here */
|
||||
#else
|
||||
/* Platform: Archos Jukebox
|
||||
* We begin with some tricks. If we have built our code to be loaded
|
||||
* via the standalone GDB stub, we will have out VBR at some other
|
||||
* location than 0x9000000. We must copy the trap vectors for the
|
||||
* GDB stub to our vector table.
|
||||
* If, on the other hand, we are running standalone we will have
|
||||
* the VBR at 0x9000000, and the copy will not do any harm.
|
||||
*/
|
||||
mov.l vbr_k,r1
|
||||
mov.l orig_vbr_k,r2
|
||||
|
||||
/* Move the invalid instruction vector (4) */
|
||||
mov #4,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the invalid slot vector (6) */
|
||||
mov #6,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the bus error vector (9) */
|
||||
mov #9,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the DMA bus error vector (10) */
|
||||
mov #10,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the NMI vector as well (11) */
|
||||
mov #11,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the breakpoint trap vector (32) */
|
||||
mov #32,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the IO trap vector (33) */
|
||||
mov #33,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the serial Rx interrupt vector (105) */
|
||||
mov #105,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
/* Platform: Archos Jukebox
|
||||
* We begin with some tricks. If we have built our code to be loaded
|
||||
* via the standalone GDB stub, we will have out VBR at some other
|
||||
* location than 0x9000000. We must copy the trap vectors for the
|
||||
* GDB stub to our vector table.
|
||||
* If, on the other hand, we are running standalone we will have
|
||||
* the VBR at 0x9000000, and the copy will not do any harm.
|
||||
*/
|
||||
mov.l vbr_k,r1
|
||||
mov.l orig_vbr_k,r2
|
||||
|
||||
/* Move the single step trap vector (127) */
|
||||
mov #127,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
ldc r1,vbr
|
||||
/* Move the invalid instruction vector (4) */
|
||||
mov #4,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Now let's get on with the normal business */
|
||||
mov.l stack_k,r15
|
||||
/* Move the invalid slot vector (6) */
|
||||
mov #6,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* zero out bss */
|
||||
mov.l edata_k,r0
|
||||
mov.l end_k,r1
|
||||
mov #0,r2
|
||||
/* Move the bus error vector (9) */
|
||||
mov #9,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the DMA bus error vector (10) */
|
||||
mov #10,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the NMI vector as well (11) */
|
||||
mov #11,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the breakpoint trap vector (32) */
|
||||
mov #32,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the IO trap vector (33) */
|
||||
mov #33,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the serial Rx interrupt vector (105) */
|
||||
mov #105,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
/* Move the single step trap vector (127) */
|
||||
mov #127,r0
|
||||
shll2 r0
|
||||
mov.l @(r0,r2),r3
|
||||
mov.l r3,@(r0,r1)
|
||||
|
||||
ldc r1,vbr
|
||||
|
||||
/* Now let's get on with the normal business */
|
||||
mov.l stack_k,r15
|
||||
|
||||
/* zero out bss */
|
||||
mov.l edata_k,r0
|
||||
mov.l end_k,r1
|
||||
mov #0,r2
|
||||
start_l:
|
||||
mov.l r2,@r0
|
||||
add #4,r0
|
||||
cmp/ge r1,r0
|
||||
bf start_l
|
||||
nop
|
||||
mov.l r2,@r0
|
||||
add #4,r0
|
||||
cmp/ge r1,r0
|
||||
bf start_l
|
||||
nop
|
||||
|
||||
/* copy the .iram section */
|
||||
mov.l iramcopy_k,r0
|
||||
mov.l iram_k,r1
|
||||
mov.l iramend_k,r2
|
||||
/* copy the .iram section */
|
||||
mov.l iramcopy_k,r0
|
||||
mov.l iram_k,r1
|
||||
mov.l iramend_k,r2
|
||||
copy_l:
|
||||
mov.l @r0,r3
|
||||
mov.l r3,@r1
|
||||
add #4,r0
|
||||
add #4,r1
|
||||
cmp/ge r2,r1
|
||||
bf copy_l
|
||||
nop
|
||||
mov.l @r0,r3
|
||||
mov.l r3,@r1
|
||||
add #4,r0
|
||||
add #4,r1
|
||||
cmp/ge r2,r1
|
||||
bf copy_l
|
||||
nop
|
||||
|
||||
/* copy the .data section, for rombased execution */
|
||||
mov.l datacopy_k,r0
|
||||
mov.l data_k,r1
|
||||
mov.l dataend_k,r2
|
||||
/* Don't copy if src and dest are equal */
|
||||
cmp/eq r0,r1
|
||||
bt nodatacopy
|
||||
/* copy the .data section, for rombased execution */
|
||||
mov.l datacopy_k,r0
|
||||
mov.l data_k,r1
|
||||
mov.l dataend_k,r2
|
||||
/* Don't copy if src and dest are equal */
|
||||
cmp/eq r0,r1
|
||||
bt nodatacopy
|
||||
copy_l2:
|
||||
mov.l @r0,r3
|
||||
mov.l r3,@r1
|
||||
add #4,r0
|
||||
add #4,r1
|
||||
cmp/ge r2,r1
|
||||
bf copy_l2
|
||||
nop
|
||||
mov.l @r0,r3
|
||||
mov.l r3,@r1
|
||||
add #4,r0
|
||||
add #4,r1
|
||||
cmp/ge r2,r1
|
||||
bf copy_l2
|
||||
nop
|
||||
nodatacopy:
|
||||
/* Munge the main thread stack */
|
||||
mov.l stack_k,r2
|
||||
mov.l deadbeef_k,r0
|
||||
mov.l stackbegin_k,r1
|
||||
/* Munge the main thread stack */
|
||||
mov.l stack_k,r2
|
||||
mov.l deadbeef_k,r0
|
||||
mov.l stackbegin_k,r1
|
||||
munge_loop:
|
||||
mov.l r0,@r1
|
||||
add #4,r1
|
||||
cmp/ge r2,r1
|
||||
bf munge_loop
|
||||
nop
|
||||
mov.l r0,@r1
|
||||
add #4,r1
|
||||
cmp/ge r2,r1
|
||||
bf munge_loop
|
||||
nop
|
||||
|
||||
mov #0,r0
|
||||
ldc r0,gbr
|
||||
|
||||
! call the mainline
|
||||
mov.l main_k,r0
|
||||
jsr @r0
|
||||
nop
|
||||
mov #0,r0
|
||||
ldc r0,gbr
|
||||
|
||||
! call the mainline
|
||||
mov.l main_k,r0
|
||||
jsr @r0
|
||||
nop
|
||||
.hoo:
|
||||
bra .hoo
|
||||
bra .hoo
|
||||
|
||||
.align 2
|
||||
.align 2
|
||||
stack_k:
|
||||
.long _stackend
|
||||
.long _stackend
|
||||
stackbegin_k:
|
||||
.long _stackbegin
|
||||
.long _stackbegin
|
||||
deadbeef_k:
|
||||
.long 0xdeadbeef
|
||||
.long 0xdeadbeef
|
||||
edata_k:
|
||||
.long _edata
|
||||
.long _edata
|
||||
end_k:
|
||||
.long _end
|
||||
.long _end
|
||||
iramcopy_k:
|
||||
.long _iramcopy
|
||||
.long _iramcopy
|
||||
iram_k:
|
||||
.long _iramstart
|
||||
.long _iramstart
|
||||
iramend_k:
|
||||
.long _iramend
|
||||
.long _iramend
|
||||
datacopy_k:
|
||||
.long _datacopy
|
||||
.long _datacopy
|
||||
data_k:
|
||||
.long _datastart
|
||||
.long _datastart
|
||||
dataend_k:
|
||||
.long _dataend
|
||||
.long _dataend
|
||||
main_k:
|
||||
.long _main
|
||||
.long _main
|
||||
vbr_k:
|
||||
.long vectors
|
||||
.long vectors
|
||||
orig_vbr_k:
|
||||
.long 0x9000000
|
||||
.long 0x9000000
|
||||
|
||||
.section .resetvectors
|
||||
.section .resetvectors
|
||||
vectors:
|
||||
.long start
|
||||
.long _stackend
|
||||
.long start
|
||||
.long _stackend
|
||||
.long start
|
||||
.long _stackend
|
||||
.long start
|
||||
.long _stackend
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue