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Minor MMU fixes

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11984 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Greg White 2007-01-11 10:28:33 +00:00
parent ffb50d07af
commit 05e2d47c9f
1 changed files with 13 additions and 15 deletions
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22
firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c
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@ -87,14 +87,14 @@ static void enable_mmu(void) {
/* Invalidate DCache for this range */ /* Invalidate DCache for this range */
/* Will do write back */ /* Will do write back */
void invalidate_dcache_range(const void *base, unsigned int size) { void invalidate_dcache_range(const void *base, unsigned int size) {
unsigned int addr = ((int) base) & ~31; unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/
unsigned int end = addr+size+32; unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */
asm volatile( asm volatile(
"inv_start: \n" "inv_start: \n"
"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
"add %0, %0, #32 \n" "add %0, %0, #32 \n"
"cmp %0, %1 \n" "cmp %0, %1 \n"
"ble inv_start \n" "bne inv_start \n"
"mov %0, #0\n" "mov %0, #0\n"
"mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */ "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
: : "r" (addr), "r" (end)); : : "r" (addr), "r" (end));
@ -123,18 +123,16 @@ void dump_dcache_range(const void *base, unsigned int size) {
unsigned int addr = (int) base; unsigned int addr = (int) base;
unsigned int end = addr+size; unsigned int end = addr+size;
asm volatile( asm volatile(
"tst %0, #31 \n" "tst %0, #31 \n" /* Check to see if low five bits are set */
"bic %0, %0, #31 \n" "bic %0, %0, #31 \n" /* Clear them */
"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */
"add %0, %0, #32 \n" "add %0, %0, #32 \n" /* Move to the next cache line */
"tst %1, #31 \n" "tst %1, #31 \n" /* Check last line for bits set */
"bic %1, %1, #31 \n" "bic %1, %1, #31 \n" /* Clear those bits */
"mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */ "mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */
"cmp %0, %1 \n"
"beq dump_end \n"
"dump_start: \n" "dump_start: \n"
"mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */ "mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */
"add %0, %0, #32 \n" "add %0, %0, #32 \n" /* Next cache line */
"cmp %0, %1 \n" "cmp %0, %1 \n"
"bne dump_start \n" "bne dump_start \n"
"dump_end: \n" "dump_end: \n"