forked from len0rd/rockbox
Clean unused stuff out of thread.h and config.h and reorganize thread-pp.c to simplify the preprocessor blocks.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26743 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
863891ce9a
commit
05ca8978c4
3 changed files with 309 additions and 416 deletions
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@ -793,11 +793,6 @@ Lyre prototype 1 */
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#define FORCE_SINGLE_CORE
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#endif
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/* Core locking types - specifies type of atomic operation */
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#define CORELOCK_NONE 0
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#define SW_CORELOCK 1 /* Mutual exclusion provided by a software algorithm
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and not a special semaphore instruction */
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#if defined(CPU_PP)
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#define IDLE_STACK_SIZE 0x80
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#define IDLE_STACK_WORDS 0x20
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@ -811,6 +806,7 @@ Lyre prototype 1 */
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#if !defined(FORCE_SINGLE_CORE)
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#define NUM_CORES 2
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#define HAVE_CORELOCK_OBJECT
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#define CURRENT_CORE current_core()
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/* Attributes for core-shared data in DRAM where IRAM is better used for other
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* purposes. */
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@ -821,9 +817,7 @@ Lyre prototype 1 */
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#define IF_COP_VOID(...) __VA_ARGS__
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#define IF_COP_CORE(core) core
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#define CONFIG_CORELOCK SW_CORELOCK /* SWP(B) is broken */
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#endif /* !defined(BOOTLOADER) && CONFIG_CPU != PP5002 */
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#endif /* !defined(FORCE_SINGLE_CORE) */
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#endif /* CPU_PP */
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@ -832,18 +826,6 @@ Lyre prototype 1 */
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#define NOCACHEDATA_ATTR __attribute__((section(".ncdata"),nocommon))
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#endif
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#ifndef CONFIG_CORELOCK
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#define CONFIG_CORELOCK CORELOCK_NONE
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#endif
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#if CONFIG_CORELOCK == SW_CORELOCK
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#define IF_SWCL(...) __VA_ARGS__
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#define IFN_SWCL(...)
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#else
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#define IF_SWCL(...)
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#define IFN_SWCL(...) __VA_ARGS__
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#endif /* CONFIG_CORELOCK == */
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#ifndef NUM_CORES
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/* Default to single core */
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#define NUM_CORES 1
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@ -855,7 +837,6 @@ Lyre prototype 1 */
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#define NOCACHEBSS_ATTR
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#define NOCACHEDATA_ATTR
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#endif
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#define CONFIG_CORELOCK CORELOCK_NONE
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#define IF_COP(...)
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#define IF_COP_VOID(...) void
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@ -109,6 +109,23 @@ struct regs
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uint32_t lr; /* 36 - r14 (lr) */
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uint32_t start; /* 40 - Thread start address, or NULL when started */
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};
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#ifdef CPU_PP
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#ifdef HAVE_CORELOCK_OBJECT
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/* No reliable atomic instruction available - use Peterson's algorithm */
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struct corelock
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{
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volatile unsigned char myl[NUM_CORES];
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volatile unsigned char turn;
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} __attribute__((packed));
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/* Too big to inline everywhere */
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void corelock_init(struct corelock *cl);
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void corelock_lock(struct corelock *cl);
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int corelock_try_lock(struct corelock *cl);
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void corelock_unlock(struct corelock *cl);
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#endif /* HAVE_CORELOCK_OBJECT */
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#endif /* CPU_PP */
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#elif defined(CPU_MIPS)
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struct regs
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{
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@ -162,26 +179,13 @@ struct thread_list
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struct thread_entry *next; /* Next thread in a list */
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};
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/* Small objects for core-wise mutual exclusion */
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#if CONFIG_CORELOCK == SW_CORELOCK
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/* No reliable atomic instruction available - use Peterson's algorithm */
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struct corelock
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{
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volatile unsigned char myl[NUM_CORES];
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volatile unsigned char turn;
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} __attribute__((packed));
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void corelock_init(struct corelock *cl);
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void corelock_lock(struct corelock *cl);
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int corelock_try_lock(struct corelock *cl);
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void corelock_unlock(struct corelock *cl);
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#else
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#ifndef HAVE_CORELOCK_OBJECT
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/* No atomic corelock op needed or just none defined */
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#define corelock_init(cl)
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#define corelock_lock(cl)
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#define corelock_try_lock(cl)
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#define corelock_unlock(cl)
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#endif /* core locking selection */
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#endif /* HAVE_CORELOCK_OBJECT */
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#ifdef HAVE_PRIORITY_SCHEDULING
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struct blocker
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@ -341,98 +345,6 @@ struct core_entry
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#define IFN_PRIO(...) __VA_ARGS__
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#endif
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/* Macros generate better code than an inline function is this case */
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#if defined (CPU_ARM)
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/* atomic */
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#if CONFIG_CORELOCK == SW_CORELOCK
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#define test_and_set(a, v, cl) \
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xchg8((a), (v), (cl))
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/* atomic */
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#define xchg8(a, v, cl) \
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({ uint32_t o; \
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corelock_lock(cl); \
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o = *(uint8_t *)(a); \
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*(uint8_t *)(a) = (v); \
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corelock_unlock(cl); \
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o; })
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#define xchg32(a, v, cl) \
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({ uint32_t o; \
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corelock_lock(cl); \
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o = *(uint32_t *)(a); \
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*(uint32_t *)(a) = (v); \
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corelock_unlock(cl); \
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o; })
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#define xchgptr(a, v, cl) \
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({ typeof (*(a)) o; \
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corelock_lock(cl); \
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o = *(a); \
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*(a) = (v); \
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corelock_unlock(cl); \
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o; })
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#endif /* locking selection */
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#elif defined (CPU_COLDFIRE)
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/* atomic */
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/* one branch will be optimized away if v is a constant expression */
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#define test_and_set(a, v, ...) \
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({ uint32_t o = 0; \
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if (v) { \
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asm volatile ( \
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"bset.b #0, (%0)" \
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: : "a"((uint8_t*)(a)) \
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: "cc"); \
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} else { \
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asm volatile ( \
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"bclr.b #0, (%0)" \
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: : "a"((uint8_t*)(a)) \
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: "cc"); \
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} \
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asm volatile ("sne.b %0" \
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: "+d"(o)); \
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o; })
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#elif CONFIG_CPU == SH7034
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/* atomic */
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#define test_and_set(a, v, ...) \
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({ uint32_t o; \
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asm volatile ( \
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"tas.b @%2 \n" \
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"mov #-1, %0 \n" \
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"negc %0, %0 \n" \
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: "=r"(o) \
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: "M"((uint32_t)(v)), /* Value of_v must be 1 */ \
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"r"((uint8_t *)(a))); \
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o; })
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#endif /* CONFIG_CPU == */
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/* defaults for no asm version */
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#ifndef test_and_set
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/* not atomic */
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#define test_and_set(a, v, ...) \
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({ uint32_t o = *(uint8_t *)(a); \
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*(uint8_t *)(a) = (v); \
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o; })
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#endif /* test_and_set */
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#ifndef xchg8
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/* not atomic */
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#define xchg8(a, v, ...) \
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({ uint32_t o = *(uint8_t *)(a); \
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*(uint8_t *)(a) = (v); \
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o; })
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#endif /* xchg8 */
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#ifndef xchg32
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/* not atomic */
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#define xchg32(a, v, ...) \
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({ uint32_t o = *(uint32_t *)(a); \
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*(uint32_t *)(a) = (v); \
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o; })
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#endif /* xchg32 */
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#ifndef xchgptr
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/* not atomic */
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#define xchgptr(a, v, ...) \
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({ typeof (*(a)) o = *(a); \
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*(a) = (v); \
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o; })
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#endif /* xchgptr */
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void core_idle(void);
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void core_wake(IF_COP_VOID(unsigned int core));
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@ -26,7 +26,21 @@
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#define IF_NO_SKIP_YIELD(...) __VA_ARGS__
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#endif
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#if NUM_CORES > 1
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#if NUM_CORES == 1
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/* Single-core variants for FORCE_SINGLE_CORE */
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static inline void core_sleep(void)
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{
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sleep_core(CURRENT_CORE);
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enable_irq();
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}
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/* Shared single-core build debugging version */
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void core_wake(void)
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{
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/* No wakey - core already wakey (because this is it) */
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}
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#else /* NUM_CORES > 1 */
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/** Model-generic PP dual-core code **/
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extern uintptr_t cpu_idlestackbegin[];
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extern uintptr_t cpu_idlestackend[];
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extern uintptr_t cop_idlestackbegin[];
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@ -37,23 +51,7 @@ static uintptr_t * const idle_stacks[NUM_CORES] =
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[COP] = cop_idlestackbegin
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};
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#if CONFIG_CPU == PP5002
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/* Bytes to emulate the PP502x mailbox bits */
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struct core_semaphores
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{
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volatile uint8_t intend_wake; /* 00h */
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volatile uint8_t stay_awake; /* 01h */
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volatile uint8_t intend_sleep; /* 02h */
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volatile uint8_t unused; /* 03h */
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};
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static struct core_semaphores core_semaphores[NUM_CORES] IBSS_ATTR;
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#endif /* CONFIG_CPU == PP5002 */
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#endif /* NUM_CORES */
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#if CONFIG_CORELOCK == SW_CORELOCK
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/* Software core locks using Peterson's mutual exclusion algorithm */
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/* Core locks using Peterson's mutual exclusion algorithm */
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/*---------------------------------------------------------------------------
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* Initialize the corelock structure.
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@ -69,8 +67,7 @@ void corelock_init(struct corelock *cl)
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* Wait for the corelock to become free and acquire it when it does.
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*---------------------------------------------------------------------------
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*/
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void corelock_lock(struct corelock *cl) __attribute__((naked));
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void corelock_lock(struct corelock *cl)
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void __attribute__((naked)) corelock_lock(struct corelock *cl)
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{
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/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
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asm volatile (
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@ -96,8 +93,7 @@ void corelock_lock(struct corelock *cl)
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* Try to aquire the corelock. If free, caller gets it, otherwise return 0.
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*---------------------------------------------------------------------------
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*/
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int corelock_try_lock(struct corelock *cl) __attribute__((naked));
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int corelock_try_lock(struct corelock *cl)
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int __attribute__((naked)) corelock_try_lock(struct corelock *cl)
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{
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/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
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asm volatile (
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@ -125,8 +121,7 @@ int corelock_try_lock(struct corelock *cl)
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* Release ownership of the corelock
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*---------------------------------------------------------------------------
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*/
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void corelock_unlock(struct corelock *cl) __attribute__((naked));
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void corelock_unlock(struct corelock *cl)
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void __attribute__((naked)) corelock_unlock(struct corelock *cl)
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{
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asm volatile (
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"mov r1, %0 \n" /* r1 = PROCESSOR_ID */
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@ -138,11 +133,9 @@ void corelock_unlock(struct corelock *cl)
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);
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(void)cl;
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}
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#else /* C versions for reference */
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/*---------------------------------------------------------------------------
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* Wait for the corelock to become free and aquire it when it does.
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*---------------------------------------------------------------------------
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*/
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void corelock_lock(struct corelock *cl)
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{
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const unsigned int core = CURRENT_CORE;
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@ -158,10 +151,6 @@ void corelock_lock(struct corelock *cl)
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}
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}
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/*---------------------------------------------------------------------------
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* Try to aquire the corelock. If free, caller gets it, otherwise return 0.
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*---------------------------------------------------------------------------
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*/
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int corelock_try_lock(struct corelock *cl)
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{
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const unsigned int core = CURRENT_CORE;
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@ -179,256 +168,36 @@ int corelock_try_lock(struct corelock *cl)
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return 0;
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}
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/*---------------------------------------------------------------------------
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* Release ownership of the corelock
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*---------------------------------------------------------------------------
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*/
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void corelock_unlock(struct corelock *cl)
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{
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cl->myl[CURRENT_CORE] = 0;
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}
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#endif /* ASM / C selection */
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#endif /* CONFIG_CORELOCK == SW_CORELOCK */
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/*---------------------------------------------------------------------------
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* Put core in a power-saving state if waking list wasn't repopulated and if
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* no other core requested a wakeup for it to perform a task.
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* Do any device-specific inits for the threads and synchronize the kernel
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* initializations.
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*---------------------------------------------------------------------------
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*/
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static void INIT_ATTR core_thread_init(unsigned int core)
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{
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if (core == CPU)
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{
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/* Wake up coprocessor and let it initialize kernel and threads */
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#ifdef CPU_PP502x
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#if NUM_CORES == 1
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static inline void core_sleep(void)
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{
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sleep_core(CURRENT_CORE);
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enable_irq();
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}
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#else
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static inline void core_sleep(unsigned int core)
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{
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#if 1
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asm volatile (
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"mov r0, #4 \n" /* r0 = 0x4 << core */
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"mov r0, r0, lsl %[c] \n"
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"str r0, [%[mbx], #4] \n" /* signal intent to sleep */
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"ldr r1, [%[mbx], #0] \n" /* && !(MBX_MSG_STAT & (0x10<<core)) ? */
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"tst r1, r0, lsl #2 \n"
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"moveq r1, #0x80000000 \n" /* Then sleep */
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"streq r1, [%[ctl], %[c], lsl #2] \n"
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"moveq r1, #0 \n" /* Clear control reg */
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"streq r1, [%[ctl], %[c], lsl #2] \n"
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"orr r1, r0, r0, lsl #2 \n" /* Signal intent to wake - clear wake flag */
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"str r1, [%[mbx], #8] \n"
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"1: \n" /* Wait for wake procedure to finish */
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"ldr r1, [%[mbx], #0] \n"
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"tst r1, r0, lsr #2 \n"
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"bne 1b \n"
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:
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: [ctl]"r"(&CPU_CTL), [mbx]"r"(MBX_BASE), [c]"r"(core)
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: "r0", "r1");
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#else /* C version for reference */
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/* Signal intent to sleep */
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MBX_MSG_SET = 0x4 << core;
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/* Something waking or other processor intends to wake us? */
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if ((MBX_MSG_STAT & (0x10 << core)) == 0)
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{
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sleep_core(core);
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wake_core(core);
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MBX_MSG_CLR = 0x3f;
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#endif
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wake_core(COP);
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/* Sleep until COP has finished */
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sleep_core(CPU);
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}
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/* Signal wake - clear wake flag */
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MBX_MSG_CLR = 0x14 << core;
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/* Wait for other processor to finish wake procedure */
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while (MBX_MSG_STAT & (0x1 << core));
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#endif /* ASM/C selection */
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enable_irq();
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}
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#endif /* NUM_CORES */
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#elif CONFIG_CPU == PP5002
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#if NUM_CORES == 1
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static inline void core_sleep(void)
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{
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sleep_core(CURRENT_CORE);
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enable_irq();
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}
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#else
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/* PP5002 has no mailboxes - emulate using bytes */
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static inline void core_sleep(unsigned int core)
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{
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#if 1
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asm volatile (
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"mov r0, #1 \n" /* Signal intent to sleep */
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"strb r0, [%[sem], #2] \n"
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"ldrb r0, [%[sem], #1] \n" /* && stay_awake == 0? */
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"cmp r0, #0 \n"
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"bne 2f \n"
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/* Sleep: PP5002 crashes if the instruction that puts it to sleep is
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* located at 0xNNNNNNN0. 4/8/C works. This sequence makes sure
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* that the correct alternative is executed. Don't change the order
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* of the next 4 instructions! */
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"tst pc, #0x0c \n"
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"mov r0, #0xca \n"
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"strne r0, [%[ctl], %[c], lsl #2] \n"
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"streq r0, [%[ctl], %[c], lsl #2] \n"
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"nop \n" /* nop's needed because of pipeline */
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"nop \n"
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"nop \n"
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"2: \n"
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"mov r0, #0 \n" /* Clear stay_awake and sleep intent */
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"strb r0, [%[sem], #1] \n"
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"strb r0, [%[sem], #2] \n"
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"1: \n" /* Wait for wake procedure to finish */
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"ldrb r0, [%[sem], #0] \n"
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"cmp r0, #0 \n"
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"bne 1b \n"
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:
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: [sem]"r"(&core_semaphores[core]), [c]"r"(core),
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[ctl]"r"(&CPU_CTL)
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: "r0"
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);
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#else /* C version for reference */
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/* Signal intent to sleep */
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core_semaphores[core].intend_sleep = 1;
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/* Something waking or other processor intends to wake us? */
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if (core_semaphores[core].stay_awake == 0)
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else
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{
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sleep_core(core);
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||||
/* Wake the CPU and return */
|
||||
wake_core(CPU);
|
||||
}
|
||||
|
||||
/* Signal wake - clear wake flag */
|
||||
core_semaphores[core].stay_awake = 0;
|
||||
core_semaphores[core].intend_sleep = 0;
|
||||
|
||||
/* Wait for other processor to finish wake procedure */
|
||||
while (core_semaphores[core].intend_wake != 0);
|
||||
|
||||
/* Enable IRQ */
|
||||
#endif /* ASM/C selection */
|
||||
enable_irq();
|
||||
}
|
||||
#endif /* NUM_CORES */
|
||||
#endif /* PP CPU type */
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Wake another processor core that is sleeping or prevent it from doing so
|
||||
* if it was already destined. FIQ, IRQ should be disabled before calling.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
#if NUM_CORES == 1
|
||||
/* Shared single-core build debugging version */
|
||||
void core_wake(void)
|
||||
{
|
||||
/* No wakey - core already wakey */
|
||||
}
|
||||
#elif defined (CPU_PP502x)
|
||||
void core_wake(unsigned int othercore)
|
||||
{
|
||||
#if 1
|
||||
/* avoid r0 since that contains othercore */
|
||||
asm volatile (
|
||||
"mrs r3, cpsr \n" /* Disable IRQ */
|
||||
"orr r1, r3, #0x80 \n"
|
||||
"msr cpsr_c, r1 \n"
|
||||
"mov r2, #0x11 \n" /* r2 = (0x11 << othercore) */
|
||||
"mov r2, r2, lsl %[oc] \n" /* Signal intent to wake othercore */
|
||||
"str r2, [%[mbx], #4] \n"
|
||||
"1: \n" /* If it intends to sleep, let it first */
|
||||
"ldr r1, [%[mbx], #0] \n" /* (MSG_MSG_STAT & (0x4 << othercore)) != 0 ? */
|
||||
"eor r1, r1, #0xc \n"
|
||||
"tst r1, r2, lsr #2 \n"
|
||||
"ldr r1, [%[ctl], %[oc], lsl #2] \n" /* && (PROC_CTL(othercore) & PROC_SLEEP) == 0 ? */
|
||||
"tsteq r1, #0x80000000 \n"
|
||||
"beq 1b \n" /* Wait for sleep or wake */
|
||||
"tst r1, #0x80000000 \n" /* If sleeping, wake it */
|
||||
"movne r1, #0x0 \n"
|
||||
"strne r1, [%[ctl], %[oc], lsl #2] \n"
|
||||
"mov r1, r2, lsr #4 \n"
|
||||
"str r1, [%[mbx], #8] \n" /* Done with wake procedure */
|
||||
"msr cpsr_c, r3 \n" /* Restore IRQ */
|
||||
:
|
||||
: [ctl]"r"(&PROC_CTL(CPU)), [mbx]"r"(MBX_BASE),
|
||||
[oc]"r"(othercore)
|
||||
: "r1", "r2", "r3");
|
||||
#else /* C version for reference */
|
||||
/* Disable interrupts - avoid reentrancy from the tick */
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
/* Signal intent to wake other processor - set stay awake */
|
||||
MBX_MSG_SET = 0x11 << othercore;
|
||||
|
||||
/* If it intends to sleep, wait until it does or aborts */
|
||||
while ((MBX_MSG_STAT & (0x4 << othercore)) != 0 &&
|
||||
(PROC_CTL(othercore) & PROC_SLEEP) == 0);
|
||||
|
||||
/* If sleeping, wake it up */
|
||||
if (PROC_CTL(othercore) & PROC_SLEEP)
|
||||
PROC_CTL(othercore) = 0;
|
||||
|
||||
/* Done with wake procedure */
|
||||
MBX_MSG_CLR = 0x1 << othercore;
|
||||
restore_irq(oldlevel);
|
||||
#endif /* ASM/C selection */
|
||||
}
|
||||
#elif CONFIG_CPU == PP5002
|
||||
/* PP5002 has no mailboxes - emulate using bytes */
|
||||
void core_wake(unsigned int othercore)
|
||||
{
|
||||
#if 1
|
||||
/* avoid r0 since that contains othercore */
|
||||
asm volatile (
|
||||
"mrs r3, cpsr \n" /* Disable IRQ */
|
||||
"orr r1, r3, #0x80 \n"
|
||||
"msr cpsr_c, r1 \n"
|
||||
"mov r1, #1 \n" /* Signal intent to wake other core */
|
||||
"orr r1, r1, r1, lsl #8 \n" /* and set stay_awake */
|
||||
"strh r1, [%[sem], #0] \n"
|
||||
"mov r2, #0x8000 \n"
|
||||
"1: \n" /* If it intends to sleep, let it first */
|
||||
"ldrb r1, [%[sem], #2] \n" /* intend_sleep != 0 ? */
|
||||
"cmp r1, #1 \n"
|
||||
"ldr r1, [%[st]] \n" /* && not sleeping ? */
|
||||
"tsteq r1, r2, lsr %[oc] \n"
|
||||
"beq 1b \n" /* Wait for sleep or wake */
|
||||
"tst r1, r2, lsr %[oc] \n"
|
||||
"ldrne r2, =0xcf004054 \n" /* If sleeping, wake it */
|
||||
"movne r1, #0xce \n"
|
||||
"strne r1, [r2, %[oc], lsl #2] \n"
|
||||
"mov r1, #0 \n" /* Done with wake procedure */
|
||||
"strb r1, [%[sem], #0] \n"
|
||||
"msr cpsr_c, r3 \n" /* Restore IRQ */
|
||||
:
|
||||
: [sem]"r"(&core_semaphores[othercore]),
|
||||
[st]"r"(&PROC_STAT),
|
||||
[oc]"r"(othercore)
|
||||
: "r1", "r2", "r3"
|
||||
);
|
||||
#else /* C version for reference */
|
||||
/* Disable interrupts - avoid reentrancy from the tick */
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
/* Signal intent to wake other processor - set stay awake */
|
||||
core_semaphores[othercore].intend_wake = 1;
|
||||
core_semaphores[othercore].stay_awake = 1;
|
||||
|
||||
/* If it intends to sleep, wait until it does or aborts */
|
||||
while (core_semaphores[othercore].intend_sleep != 0 &&
|
||||
(PROC_STAT & PROC_SLEEPING(othercore)) == 0);
|
||||
|
||||
/* If sleeping, wake it up */
|
||||
if (PROC_STAT & PROC_SLEEPING(othercore))
|
||||
wake_core(othercore);
|
||||
|
||||
/* Done with wake procedure */
|
||||
core_semaphores[othercore].intend_wake = 0;
|
||||
restore_irq(oldlevel);
|
||||
#endif /* ASM/C selection */
|
||||
}
|
||||
#endif /* CPU type */
|
||||
|
||||
#if NUM_CORES > 1
|
||||
/*---------------------------------------------------------------------------
|
||||
* Switches to a stack that always resides in the Rockbox core.
|
||||
*
|
||||
|
|
@ -507,35 +276,266 @@ static void __attribute__((naked))
|
|||
"mov lr, pc \n"
|
||||
"bx r0 \n"
|
||||
"ldmfd sp!, { r4-r11, pc } \n" /* Restore non-volatile context to new core and return */
|
||||
".ltorg \n" /* Dump constant pool */
|
||||
: : "i"(IDLE_STACK_WORDS)
|
||||
);
|
||||
(void)core; (void)thread;
|
||||
}
|
||||
|
||||
/** PP-model-specific dual-core code **/
|
||||
|
||||
#if CONFIG_CPU == PP5002
|
||||
/* PP5002 has no mailboxes - Bytes to emulate the PP502x mailbox bits */
|
||||
struct core_semaphores
|
||||
{
|
||||
volatile uint8_t intend_wake; /* 00h */
|
||||
volatile uint8_t stay_awake; /* 01h */
|
||||
volatile uint8_t intend_sleep; /* 02h */
|
||||
volatile uint8_t unused; /* 03h */
|
||||
};
|
||||
|
||||
static struct core_semaphores core_semaphores[NUM_CORES] IBSS_ATTR;
|
||||
|
||||
#if 1 /* Select ASM */
|
||||
/*---------------------------------------------------------------------------
|
||||
* Do any device-specific inits for the threads and synchronize the kernel
|
||||
* initializations.
|
||||
* Put core in a power-saving state if waking list wasn't repopulated and if
|
||||
* no other core requested a wakeup for it to perform a task.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
static void core_thread_init(unsigned int core) INIT_ATTR;
|
||||
static void core_thread_init(unsigned int core)
|
||||
static inline void core_sleep(unsigned int core)
|
||||
{
|
||||
if (core == CPU)
|
||||
{
|
||||
/* Wake up coprocessor and let it initialize kernel and threads */
|
||||
#ifdef CPU_PP502x
|
||||
MBX_MSG_CLR = 0x3f;
|
||||
#endif
|
||||
wake_core(COP);
|
||||
/* Sleep until COP has finished */
|
||||
sleep_core(CPU);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Wake the CPU and return */
|
||||
wake_core(CPU);
|
||||
}
|
||||
asm volatile (
|
||||
"mov r0, #1 \n" /* Signal intent to sleep */
|
||||
"strb r0, [%[sem], #2] \n"
|
||||
"ldrb r0, [%[sem], #1] \n" /* && stay_awake == 0? */
|
||||
"cmp r0, #0 \n"
|
||||
"bne 2f \n"
|
||||
/* Sleep: PP5002 crashes if the instruction that puts it to sleep is
|
||||
* located at 0xNNNNNNN0. 4/8/C works. This sequence makes sure
|
||||
* that the correct alternative is executed. Don't change the order
|
||||
* of the next 4 instructions! */
|
||||
"tst pc, #0x0c \n"
|
||||
"mov r0, #0xca \n"
|
||||
"strne r0, [%[ctl], %[c], lsl #2] \n"
|
||||
"streq r0, [%[ctl], %[c], lsl #2] \n"
|
||||
"nop \n" /* nop's needed because of pipeline */
|
||||
"nop \n"
|
||||
"nop \n"
|
||||
"2: \n"
|
||||
"mov r0, #0 \n" /* Clear stay_awake and sleep intent */
|
||||
"strb r0, [%[sem], #1] \n"
|
||||
"strb r0, [%[sem], #2] \n"
|
||||
"1: \n" /* Wait for wake procedure to finish */
|
||||
"ldrb r0, [%[sem], #0] \n"
|
||||
"cmp r0, #0 \n"
|
||||
"bne 1b \n"
|
||||
:
|
||||
: [sem]"r"(&core_semaphores[core]), [c]"r"(core),
|
||||
[ctl]"r"(&CPU_CTL)
|
||||
: "r0"
|
||||
);
|
||||
enable_irq();
|
||||
}
|
||||
#endif /* NUM_CORES */
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Wake another processor core that is sleeping or prevent it from doing so
|
||||
* if it was already destined. FIQ, IRQ should be disabled before calling.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
void core_wake(unsigned int othercore)
|
||||
{
|
||||
/* avoid r0 since that contains othercore */
|
||||
asm volatile (
|
||||
"mrs r3, cpsr \n" /* Disable IRQ */
|
||||
"orr r1, r3, #0x80 \n"
|
||||
"msr cpsr_c, r1 \n"
|
||||
"mov r1, #1 \n" /* Signal intent to wake other core */
|
||||
"orr r1, r1, r1, lsl #8 \n" /* and set stay_awake */
|
||||
"strh r1, [%[sem], #0] \n"
|
||||
"mov r2, #0x8000 \n"
|
||||
"1: \n" /* If it intends to sleep, let it first */
|
||||
"ldrb r1, [%[sem], #2] \n" /* intend_sleep != 0 ? */
|
||||
"cmp r1, #1 \n"
|
||||
"ldr r1, [%[st]] \n" /* && not sleeping ? */
|
||||
"tsteq r1, r2, lsr %[oc] \n"
|
||||
"beq 1b \n" /* Wait for sleep or wake */
|
||||
"tst r1, r2, lsr %[oc] \n"
|
||||
"ldrne r2, =0xcf004054 \n" /* If sleeping, wake it */
|
||||
"movne r1, #0xce \n"
|
||||
"strne r1, [r2, %[oc], lsl #2] \n"
|
||||
"mov r1, #0 \n" /* Done with wake procedure */
|
||||
"strb r1, [%[sem], #0] \n"
|
||||
"msr cpsr_c, r3 \n" /* Restore IRQ */
|
||||
:
|
||||
: [sem]"r"(&core_semaphores[othercore]),
|
||||
[st]"r"(&PROC_STAT),
|
||||
[oc]"r"(othercore)
|
||||
: "r1", "r2", "r3"
|
||||
);
|
||||
}
|
||||
|
||||
#else /* C version for reference */
|
||||
|
||||
static inline void core_sleep(unsigned int core)
|
||||
{
|
||||
/* Signal intent to sleep */
|
||||
core_semaphores[core].intend_sleep = 1;
|
||||
|
||||
/* Something waking or other processor intends to wake us? */
|
||||
if (core_semaphores[core].stay_awake == 0)
|
||||
{
|
||||
sleep_core(core);
|
||||
}
|
||||
|
||||
/* Signal wake - clear wake flag */
|
||||
core_semaphores[core].stay_awake = 0;
|
||||
core_semaphores[core].intend_sleep = 0;
|
||||
|
||||
/* Wait for other processor to finish wake procedure */
|
||||
while (core_semaphores[core].intend_wake != 0);
|
||||
|
||||
/* Enable IRQ */
|
||||
enable_irq();
|
||||
}
|
||||
|
||||
void core_wake(unsigned int othercore)
|
||||
{
|
||||
/* Disable interrupts - avoid reentrancy from the tick */
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
/* Signal intent to wake other processor - set stay awake */
|
||||
core_semaphores[othercore].intend_wake = 1;
|
||||
core_semaphores[othercore].stay_awake = 1;
|
||||
|
||||
/* If it intends to sleep, wait until it does or aborts */
|
||||
while (core_semaphores[othercore].intend_sleep != 0 &&
|
||||
(PROC_STAT & PROC_SLEEPING(othercore)) == 0);
|
||||
|
||||
/* If sleeping, wake it up */
|
||||
if (PROC_STAT & PROC_SLEEPING(othercore))
|
||||
wake_core(othercore);
|
||||
|
||||
/* Done with wake procedure */
|
||||
core_semaphores[othercore].intend_wake = 0;
|
||||
restore_irq(oldlevel);
|
||||
}
|
||||
#endif /* ASM/C selection */
|
||||
|
||||
#elif defined (CPU_PP502x)
|
||||
|
||||
#if 1 /* Select ASM */
|
||||
/*---------------------------------------------------------------------------
|
||||
* Put core in a power-saving state if waking list wasn't repopulated and if
|
||||
* no other core requested a wakeup for it to perform a task.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void core_sleep(unsigned int core)
|
||||
{
|
||||
asm volatile (
|
||||
"mov r0, #4 \n" /* r0 = 0x4 << core */
|
||||
"mov r0, r0, lsl %[c] \n"
|
||||
"str r0, [%[mbx], #4] \n" /* signal intent to sleep */
|
||||
"ldr r1, [%[mbx], #0] \n" /* && !(MBX_MSG_STAT & (0x10<<core)) ? */
|
||||
"tst r1, r0, lsl #2 \n"
|
||||
"moveq r1, #0x80000000 \n" /* Then sleep */
|
||||
"streq r1, [%[ctl], %[c], lsl #2] \n"
|
||||
"moveq r1, #0 \n" /* Clear control reg */
|
||||
"streq r1, [%[ctl], %[c], lsl #2] \n"
|
||||
"orr r1, r0, r0, lsl #2 \n" /* Signal intent to wake - clear wake flag */
|
||||
"str r1, [%[mbx], #8] \n"
|
||||
"1: \n" /* Wait for wake procedure to finish */
|
||||
"ldr r1, [%[mbx], #0] \n"
|
||||
"tst r1, r0, lsr #2 \n"
|
||||
"bne 1b \n"
|
||||
:
|
||||
: [ctl]"r"(&CPU_CTL), [mbx]"r"(MBX_BASE), [c]"r"(core)
|
||||
: "r0", "r1");
|
||||
enable_irq();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Wake another processor core that is sleeping or prevent it from doing so
|
||||
* if it was already destined. FIQ, IRQ should be disabled before calling.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
void core_wake(unsigned int othercore)
|
||||
{
|
||||
/* avoid r0 since that contains othercore */
|
||||
asm volatile (
|
||||
"mrs r3, cpsr \n" /* Disable IRQ */
|
||||
"orr r1, r3, #0x80 \n"
|
||||
"msr cpsr_c, r1 \n"
|
||||
"mov r2, #0x11 \n" /* r2 = (0x11 << othercore) */
|
||||
"mov r2, r2, lsl %[oc] \n" /* Signal intent to wake othercore */
|
||||
"str r2, [%[mbx], #4] \n"
|
||||
"1: \n" /* If it intends to sleep, let it first */
|
||||
"ldr r1, [%[mbx], #0] \n" /* (MSG_MSG_STAT & (0x4 << othercore)) != 0 ? */
|
||||
"eor r1, r1, #0xc \n"
|
||||
"tst r1, r2, lsr #2 \n"
|
||||
"ldr r1, [%[ctl], %[oc], lsl #2] \n" /* && (PROC_CTL(othercore) & PROC_SLEEP) == 0 ? */
|
||||
"tsteq r1, #0x80000000 \n"
|
||||
"beq 1b \n" /* Wait for sleep or wake */
|
||||
"tst r1, #0x80000000 \n" /* If sleeping, wake it */
|
||||
"movne r1, #0x0 \n"
|
||||
"strne r1, [%[ctl], %[oc], lsl #2] \n"
|
||||
"mov r1, r2, lsr #4 \n"
|
||||
"str r1, [%[mbx], #8] \n" /* Done with wake procedure */
|
||||
"msr cpsr_c, r3 \n" /* Restore IRQ */
|
||||
:
|
||||
: [ctl]"r"(&PROC_CTL(CPU)), [mbx]"r"(MBX_BASE),
|
||||
[oc]"r"(othercore)
|
||||
: "r1", "r2", "r3");
|
||||
}
|
||||
|
||||
#else /* C version for reference */
|
||||
|
||||
static inline void core_sleep(unsigned int core)
|
||||
{
|
||||
/* Signal intent to sleep */
|
||||
MBX_MSG_SET = 0x4 << core;
|
||||
|
||||
/* Something waking or other processor intends to wake us? */
|
||||
if ((MBX_MSG_STAT & (0x10 << core)) == 0)
|
||||
{
|
||||
sleep_core(core);
|
||||
wake_core(core);
|
||||
}
|
||||
|
||||
/* Signal wake - clear wake flag */
|
||||
MBX_MSG_CLR = 0x14 << core;
|
||||
|
||||
/* Wait for other processor to finish wake procedure */
|
||||
while (MBX_MSG_STAT & (0x1 << core));
|
||||
enable_irq();
|
||||
}
|
||||
|
||||
void core_wake(unsigned int othercore)
|
||||
{
|
||||
/* Disable interrupts - avoid reentrancy from the tick */
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
/* Signal intent to wake other processor - set stay awake */
|
||||
MBX_MSG_SET = 0x11 << othercore;
|
||||
|
||||
/* If it intends to sleep, wait until it does or aborts */
|
||||
while ((MBX_MSG_STAT & (0x4 << othercore)) != 0 &&
|
||||
(PROC_CTL(othercore) & PROC_SLEEP) == 0);
|
||||
|
||||
/* If sleeping, wake it up */
|
||||
if (PROC_CTL(othercore) & PROC_SLEEP)
|
||||
PROC_CTL(othercore) = 0;
|
||||
|
||||
/* Done with wake procedure */
|
||||
MBX_MSG_CLR = 0x1 << othercore;
|
||||
restore_irq(oldlevel);
|
||||
}
|
||||
#endif /* ASM/C selection */
|
||||
|
||||
#endif /* CPU_PPxxxx */
|
||||
|
||||
/* Keep constant pool in range of inline ASM */
|
||||
static void __attribute__((naked, used)) dump_ltorg(void)
|
||||
{
|
||||
asm volatile (".ltorg");
|
||||
}
|
||||
|
||||
#endif /* NUM_CORES */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue