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Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-04-06 04:34:57 +00:00
parent be698f086d
commit 05099149f1
40 changed files with 323 additions and 126 deletions
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4
firmware/thread.c
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@ -235,7 +235,7 @@ extern uintptr_t cpu_idlestackbegin[];
extern uintptr_t cpu_idlestackend[];
extern uintptr_t cop_idlestackbegin[];
extern uintptr_t cop_idlestackend[];
static uintptr_t * const idle_stacks[NUM_CORES] NOCACHEDATA_ATTR =
static uintptr_t * const idle_stacks[NUM_CORES] =
{
[CPU] = cpu_idlestackbegin,
[COP] = cop_idlestackbegin
@ -251,7 +251,7 @@ struct core_semaphores
volatile uint8_t unused; /* 03h */
};
static struct core_semaphores core_semaphores[NUM_CORES] NOCACHEBSS_ATTR;
static struct core_semaphores core_semaphores[NUM_CORES] IBSS_ATTR;
#endif /* CONFIG_CPU == PP5002 */
#endif /* NUM_CORES */