forked from len0rd/rockbox
Revert accidental changes from r24723
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24724 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
parent
e5c815272d
commit
04ea85fb88
8 changed files with 56 additions and 67 deletions
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@ -179,14 +179,3 @@ md5sum.c
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#ifdef USB_ENABLE_HID
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#ifdef USB_ENABLE_HID
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remote_control.c
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remote_control.c
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#endif
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#endif
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test_codec.c
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test_core_jpeg.c
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test_disk.c
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test_fps.c
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test_gfx.c
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test_mem_jpeg.c
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test_resize.c
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test_sampr.c
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test_scanrate.c
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test_viewports.c
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@ -30,7 +30,7 @@ PLUGIN_HEADER
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#define EV_EXIT 1337
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#define EV_EXIT 1337
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/* seems to work with 1300, but who knows... */
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/* seems to work with 1300, but who knows... */
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#define THREAD_STACK_SIZE DEFAULT_STACK_SIZE + 0x1200
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#define THREAD_STACK_SIZE DEFAULT_STACK_SIZE + 0x200
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#if CONFIG_KEYPAD == RECORDER_PAD
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#if CONFIG_KEYPAD == RECORDER_PAD
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@ -10,7 +10,7 @@
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DOOMSRCDIR := $(APPSDIR)/plugins/doom
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DOOMSRCDIR := $(APPSDIR)/plugins/doom
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DOOMBUILDDIR := $(BUILDDIR)/apps/plugins/doom
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DOOMBUILDDIR := $(BUILDDIR)/apps/plugins/doom
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#ROCKS += $(DOOMBUILDDIR)/doom.rock
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ROCKS += $(DOOMBUILDDIR)/doom.rock
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DOOM_SRC := $(call preprocess, $(DOOMSRCDIR)/SOURCES)
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DOOM_SRC := $(call preprocess, $(DOOMSRCDIR)/SOURCES)
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DOOM_SRC += $(ROOTDIR)/firmware/common/sscanf.c
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DOOM_SRC += $(ROOTDIR)/firmware/common/sscanf.c
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@ -142,8 +142,8 @@ OUTPUT_FORMAT(elf32-littlemips)
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#elif CONFIG_CPU==S5L8700
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#elif CONFIG_CPU==S5L8700
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#define DRAMORIG 0x08000000
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#define DRAMORIG 0x08000000
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#define IRAMORIG (0x00000000 + (128*1024))
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#define IRAMORIG (0x00000000 + (64*1024))
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#define IRAMSIZE (128*1024)
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#define IRAMSIZE (64*1024)
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#elif CONFIG_CPU==S5L8701
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#elif CONFIG_CPU==S5L8701
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#define DRAMORIG 0x08000000
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#define DRAMORIG 0x08000000
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@ -32,7 +32,7 @@
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#include "system.h"
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#include "system.h"
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static char panic_buf[128];
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static char panic_buf[128];
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#define LINECHARS (LCD_WIDTH/SYSFONT_WIDTH) - 2
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#define LINECHARS (LCD_WIDTH/SYSFONT_WIDTH)
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/*
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/*
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* "Dude. This is pretty fucked-up, right here."
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* "Dude. This is pretty fucked-up, right here."
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@ -28,7 +28,7 @@ STARTUP(target/arm/s5l8700/crt0.o)
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#define DRAMSIZE (DRAM_SIZE - STUBOFFSET - PLUGINSIZE - CODECSIZE)
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#define DRAMSIZE (DRAM_SIZE - STUBOFFSET - PLUGINSIZE - CODECSIZE)
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#define CODECORIG (ENDAUDIOADDR)
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#define CODECORIG (ENDAUDIOADDR)
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#if CONFIG_CPU==S5L8700
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#if CONFIG_CPU==S5L8700
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#define IRAMSIZE (128*1024) /* 256KB total - 128KB for core, 128KB for plugins */
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#define IRAMSIZE (64*1024) /* 128KB total - 64KB for core, 64KB for plugins */
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#else /* S5L8701 */
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#else /* S5L8701 */
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#define IRAMSIZE (96*1024) /* 176KB total - 96KB for core, 80KB for plugins */
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#define IRAMSIZE (96*1024) /* 176KB total - 96KB for core, 80KB for plugins */
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#endif
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#endif
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@ -108,7 +108,7 @@ SECTIONS
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stackbegin = .;
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stackbegin = .;
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_stackbegin = .;
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_stackbegin = .;
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#ifdef IPOD_NANO2G
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#ifdef IPOD_NANO2G
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. += 0x2000;
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. += 0x4000;
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#endif
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#endif
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. += 0x2000;
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. += 0x2000;
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stackend = .;
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stackend = .;
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@ -260,64 +260,64 @@ start_loc:
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#if defined(MEIZU_M6SP) || defined(MEIZU_M3)
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#if defined(MEIZU_M6SP) || defined(MEIZU_M3)
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/* setup SDRAM for Meizu M6SP */
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/* setup SDRAM for Meizu M6SP */
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ldr r1, =0x38200000
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ldr r1, =0x38200000
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// configure SDR drive strength and pad settings
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// configure SDR drive strength and pad settings
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mov r0, #SDR_DSS_SEL_B
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mov r0, #SDR_DSS_SEL_B
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str r0, [r1, #0x4C] // MIU_DSS_SEL_B
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str r0, [r1, #0x4C] // MIU_DSS_SEL_B
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mov r0, #SDR_DSS_SEL_O
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mov r0, #SDR_DSS_SEL_O
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str r0, [r1, #0x50] // MIU_DSS_SEL_O
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str r0, [r1, #0x50] // MIU_DSS_SEL_O
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mov r0, #SDR_DSS_SEL_C
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mov r0, #SDR_DSS_SEL_C
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str r0, [r1, #0x54] // MIU_DSS_SEL_C
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str r0, [r1, #0x54] // MIU_DSS_SEL_C
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mov r0, #2
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mov r0, #2
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str r0, [r1, #0x60] // SSTL2_PAD_ON
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str r0, [r1, #0x60] // SSTL2_PAD_ON
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// select SDR mode
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// select SDR mode
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ldr r0, [r1, #0x40]
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ldr r0, [r1, #0x40]
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mov r2, #0xFFFDFFFF
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mov r2, #0xFFFDFFFF
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and r0, r0, r2
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and r0, r0, r2
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orr r0, r0, #1
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orr r0, r0, #1
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str r0, [r1, #0x40] // MIUORG
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str r0, [r1, #0x40] // MIUORG
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// set controller configuration
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// set controller configuration
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mov r0, #SDR_CONFIG
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mov r0, #SDR_CONFIG
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str r0, [r1] // MIUCON
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str r0, [r1] // MIUCON
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// set SDRAM timing
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// set SDRAM timing
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ldr r0, =SDR_TIMING
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ldr r0, =SDR_TIMING
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str r0, [r1, #0x10] // MIUSDPARA
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str r0, [r1, #0x10] // MIUSDPARA
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// set refresh rate
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// set refresh rate
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mov r0, #0x1080
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mov r0, #0x1080
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str r0, [r1, #0x08] // MIUAREF
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str r0, [r1, #0x08] // MIUAREF
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// initialise SDRAM
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// initialise SDRAM
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mov r0, #0x003
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mov r0, #0x003
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str r0, [r1, #0x04] // MIUCOM = nop
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str r0, [r1, #0x04] // MIUCOM = nop
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ldr r0, =0x203
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ldr r0, =0x203
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str r0, [r1, #0x04] // MIUCOM = precharge all banks
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str r0, [r1, #0x04] // MIUCOM = precharge all banks
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nop
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nop
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nop
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nop
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nop
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nop
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ldr r0, =0x303
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ldr r0, =0x303
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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// set mode register
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// set mode register
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mov r0, #SDR_MRS
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mov r0, #SDR_MRS
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str r0, [r1, #0x0C] // MIUMRS
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str r0, [r1, #0x0C] // MIUMRS
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ldr r0, =0x103
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ldr r0, =0x103
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str r0, [r1, #0x04] // MIUCOM = mode register set
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str r0, [r1, #0x04] // MIUCOM = mode register set
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ldr r0, =SDR_EMRS
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ldr r0, =SDR_EMRS
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str r0, [r1, #0x0C] // MIUMRS
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str r0, [r1, #0x0C] // MIUMRS
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ldr r0, =0x103
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ldr r0, =0x103
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str r0, [r1, #0x04] // MIUCOM = mode register set
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str r0, [r1, #0x04] // MIUCOM = mode register set
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#endif /* MEIZU_M6SP */
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#endif /* MEIZU_M6SP */
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mov r1, #0x1
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mov r1, #0x1
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@ -48,7 +48,7 @@ void power_off(void)
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void power_init(void)
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void power_init(void)
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{
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{
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pmu_write(0x1e, 15); /* Vcore = 1.000V */
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/* TODO */
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}
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}
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#if CONFIG_CHARGING
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#if CONFIG_CHARGING
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