devs/foxbox
1
0
Fork 0
forked from len0rd/rockbox
Code Pull requests Activity

S5L870x crt0.S: Streamline things a bit, and close unneeded clock gates on iPod Nano 2G

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23098 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann 2009-10-11 09:52:39 +00:00
parent 747b9ca258
commit 0260b0ad5a
1 changed files with 26 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

57
firmware/target/arm/s5l8700/crt0.S
View file

@ -61,17 +61,13 @@ newstart2:
str r0, [r1] str r0, [r1]
mov r0, #0 mov r0, #0
ldr r1, =0x39c00008
str r0, [r1] // mask all interrupts
ldr r1, =0x39c00020
str r0, [r1] // mask all external interrupts
mvn r0, #0
ldr r1, =0x39c0001c
str r0, [r1] // clear pending external interrupts
mov r1, #0x39c00000 mov r1, #0x39c00000
str r0, [r1,#0x08] // mask all interrupts
str r0, [r1,#0x20] // mask all external interrupts
mvn r0, #0
str r0, [r1,#0x1c] // clear pending external interrupts
str r0, [r1] // irq priority str r0, [r1] // irq priority
ldr r1, =0x39c00010 str r0, [r1,#0x10] // clear pending interrupts
str r0, [r1] // clear pending interrupts
// ldr r1, =0x3cf00000 // ldr r1, =0x3cf00000
// ldr r0, [r1] // ldr r0, [r1]
@ -80,11 +76,10 @@ newstart2:
// mov r2, #0x10 // mov r2, #0x10
// orr r0, r0, r2 // orr r0, r0, r2
// str r0, [r1] // str r0, [r1]
// ldr r1, =0x3cf00004 // ldr r0, [r1,#0x04]
// ldr r0, [r1]
// mov r2, #4 // mov r2, #4
// orr r0, r0, r2 // orr r0, r0, r2
// str r0, [r1] // switch backlight on // str r0, [r1,#0x04] // switch backlight on
#if CONFIG_CPU==S5L8701 #if CONFIG_CPU==S5L8701
ldr r1, =0x38200000 ldr r1, =0x38200000
@ -109,36 +104,29 @@ start_loc:
#endif /* BOOTLOADER */ #endif /* BOOTLOADER */
#endif /* CONFIG_CPU==S5L8701 */ #endif /* CONFIG_CPU==S5L8701 */
ldr r1, =0x3c500000 // CLKCON ldr r1, =0x3c500000
ldr r0, =0x00800080 ldr r0, =0x00800080
str r0, [r1] str r0, [r1] // CLKCON
ldr r1, =0x3c500024 // PLLCON
mov r0, #0 mov r0, #0
str r0, [r1] str r0, [r1,#0x24] // PLLCON
ldr r1, =0x3c500004 // PLL0PMS
#ifdef IPOD_NANO2G #ifdef IPOD_NANO2G
ldr r0, =0x21200 // pdiv=2, mdiv=?? sdiv=0 ldr r0, =0x21200 // pdiv=2, mdiv=0x12 sdiv=0
#else #else
ldr r0, =0x1ad200 ldr r0, =0x1ad200 // pdiv=0x1a, mdiv=0xd2 sdiv=0
#endif #endif
str r0, [r1] str r0, [r1,#0x04] // PLL0PMS
ldr r1, =0x3c500014 // PLL0LCNT
ldr r0, =8100 ldr r0, =8100
str r0, [r1] str r0, [r1,#0x14] // PLL0LCNT
ldr r1, =0x3c500024 // PLLCON
mov r0, #1 mov r0, #1
str r0, [r1] str r0, [r1,#0x24] // PLLCON
ldr r1, =0x3c500020 // PLLLOCK
1: 1:
ldr r0, [r1] ldr r0, [r1,#0x20] // PLLLOCK
tst r0, #1 tst r0, #1
beq 1b beq 1b
ldr r1, =0x3c50003c // CLKCON2
mov r0, #0x80 mov r0, #0x80
str r0, [r1] str r0, [r1,#0x3c] // CLKCON2
ldr r1, =0x3c500000 // CLKCON ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
ldr r0, =0x20803180 str r0, [r1] // CLKCON
str r0, [r1] // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
ldr r2, =0xc0000078 ldr r2, =0xc0000078
mrc 15, 0, r0, c1, c0, 0 mrc 15, 0, r0, c1, c0, 0
@ -168,6 +156,13 @@ start_loc:
/* The following two sections of code (i.e. Nano2G and Meizus) should /* The following two sections of code (i.e. Nano2G and Meizus) should
be unified at some point. */ be unified at some point. */
#ifdef IPOD_NANO2G #ifdef IPOD_NANO2G
ldr r1, =0x3c500000
ldr r0, =0xffdff7ff
str r0, [r1,#0x28] // PWRCON
ldr r0, =0xffffef7e
str r0, [r1,#0x40] // PWRCONEXT
mrc 15, 0, r0, c1, c0, 0 mrc 15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000 bic r0, r0, #0x1000
bic r0, r0, #0x5 bic r0, r0, #0x5