forked from len0rd/rockbox
PNX0101: new register names and polishing support for Clock Generation Unit
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14792 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Tomasz Malesinski
parent
d14d6246c0
commit
026032f06d
2 changed files with 73 additions and 76 deletions
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@ -220,6 +220,44 @@ struct pnx0101_timer {
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#define INTREQ_WEACTVLO 0x02000000
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#define INTREQ_ENABLE 0x00010000
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/* General purpose DMA */
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struct pnx0101_dma_channel {
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unsigned long source;
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unsigned long dest;
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unsigned long length;
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unsigned long config;
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unsigned long enable;
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unsigned long pad1;
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unsigned long pad2;
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unsigned long count;
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};
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#define DMACHANNEL ((volatile struct pnx0101_dma_channel *)0x80104800)
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struct pnx0101_dma {
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unsigned long enable;
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unsigned long stat;
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unsigned long irqmask;
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unsigned long softint;
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};
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#define DMA (*(volatile struct pnx0101_dma *)0x80104c00)
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struct pnx0101_audio {
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unsigned long pad1;
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unsigned long siocr;
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unsigned long pad2;
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unsigned long pad3;
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unsigned long pad4;
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unsigned long pad5;
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unsigned long ddacctrl;
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unsigned long ddacstat;
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unsigned long ddacset;
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};
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#define AUDIO (*(volatile struct pnx0101_audio *)0x80200380)
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#endif /* ASM */
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#endif
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@ -26,13 +26,12 @@ static struct
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unsigned char freq;
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unsigned char sys_mult;
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unsigned char sys_div;
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unsigned char mem_conf[10];
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}
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perf_modes[3] ICONST_ATTR =
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{
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{12, 4, 4, {2, 1, 1, 1, 1, 1, 1, 1, 1, 0}},
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{48, 4, 1, {5, 4, 1, 4, 4, 1, 3, 3, 1, 0}},
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{60, 5, 1, {6, 5, 1, 5, 5, 1, 4, 3, 1, 1}}
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{12, 4, 4},
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{48, 4, 1},
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{60, 5, 1}
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};
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static int performance_mode, bus_divider;
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@ -89,11 +88,6 @@ static void cgu_connect_div_to_clock(int rel_div, int esr)
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CGU.clk_esr[esr] = (rel_div << 1) | 1;
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}
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static void cgu_disconnect_div_from_clock(int esr)
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{
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CGU.clk_esr[esr] = 0;
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}
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static void cgu_enable_clock(int clock)
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{
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CGU.clk_pcr[clock] |= 1;
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@ -106,63 +100,43 @@ static void cgu_start_sel_stage_dividers(int bcr)
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/* Convert a pointer that points to IRAM (0x4xxxx) to a pointer that
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points to the uncached page (0x0xxxx) that is also mapped to IRAM. */
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static inline void *noncached(void *p) {
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static inline void *noncached(void *p)
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{
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return (void *)(((unsigned long)p) & 0xffff);
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}
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/* TODO: if it works, then comment it */
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static void do_set_mem_timings(int mode) ICODE_ATTR;
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static void do_set_mem_timings(int mode)
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/* To avoid SRAM accesses while changing memory controller settings we
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run this routine from uncached copy of IRAM. All times are in CPU
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cycles. At CPU frequencies lower than 60 MHz we could use faster
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settings, but since DMA may access SRAM at any time, changing
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memory timings together with CPU frequency would be tricky. */
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static void do_set_mem_timings(void) ICODE_ATTR;
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static void do_set_mem_timings(void)
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{
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unsigned char *mem_conf = noncached(perf_modes[mode].mem_conf);
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int old_irq = set_irq_level(HIGHEST_IRQ_LEVEL);
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while ((EMC.status & 3) != 0);
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EMC.control = 5;
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EMCSTATIC0.waitrd = mem_conf[0];
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EMCSTATIC0.waitwr = mem_conf[1];
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EMCSTATIC1.waitrd = mem_conf[3];
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EMCSTATIC1.waitwr = mem_conf[4];
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EMCSTATIC2.waitrd = mem_conf[6];
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EMCSTATIC2.waitwr = mem_conf[7];
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EMCSTATIC0.waitoen = mem_conf[2];
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EMCSTATIC1.waitoen = mem_conf[5];
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EMCSTATIC2.waitoen = mem_conf[8];
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EMCSTATIC0.waitrd = 6;
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EMCSTATIC0.waitwr = 5;
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EMCSTATIC1.waitrd = 5;
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EMCSTATIC1.waitwr = 4; /* OF uses 5 here */
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EMCSTATIC2.waitrd = 4;
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EMCSTATIC2.waitwr = 3;
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EMCSTATIC0.waitoen = 1;
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EMCSTATIC1.waitoen = 1;
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EMCSTATIC2.waitoen = 1;
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/* Enable write buffers for SRAM. */
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#ifndef DEBUG
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EMCSTATIC1.config = mem_conf[9] ? 0x80081 : 0x81;
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EMCSTATIC1.config = 0x80081;
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#endif
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EMC.control = 1;
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set_irq_level(old_irq);
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}
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static void emc_set_mem_timings(int mode) {
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void (*f)(int) = noncached(do_set_mem_timings);
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(*f)(mode);
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}
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/*
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static void do_enable_write_buffers(int on) ICODE_ATTR;
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static void do_enable_write_buffers(int on) {
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int old_irq = set_irq_level(HIGHEST_IRQ_LEVEL);
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while ((EMC.status & 3) != 0);
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EMC.control = 5;
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EMCSTATIC1.config = on ? 0x80081 : 0x81;
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EMC.control = 1;
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set_irq_level(old_irq);
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}
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void emc_enable_write_buffers(int on) {
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void (*f)(int) = noncached(do_enable_write_buffers);
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(*f)(on);
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}
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*/
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/* can it be replaced? */
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static void cgu_busy_wait(int n)
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static void emc_set_mem_timings(void)
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{
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while (n > 0)
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{
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n--;
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}
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void (*f)(void) = noncached(do_set_mem_timings);
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(*f)();
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}
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static void cgu_set_sys_mult(int i)
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@ -193,22 +167,10 @@ static void cgu_set_sys_mult(int i)
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static void pnx0101_set_performance_mode(int mode)
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{
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int old = performance_mode;
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if (perf_modes[old].freq < perf_modes[mode].freq)
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{
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emc_set_mem_timings(mode);
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if (perf_modes[old].sys_mult != perf_modes[mode].sys_mult)
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cgu_set_sys_mult(perf_modes[mode].sys_mult);
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if (perf_modes[old].sys_div != perf_modes[mode].sys_div)
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cgu_configure_div(bus_divider, 1, perf_modes[mode].sys_div);
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}
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else if (perf_modes[old].freq > perf_modes[mode].freq)
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{
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if (perf_modes[old].sys_mult != perf_modes[mode].sys_mult)
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cgu_set_sys_mult(perf_modes[mode].sys_mult);
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if (perf_modes[old].sys_div != perf_modes[mode].sys_div)
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cgu_configure_div(bus_divider, 1, perf_modes[mode].sys_div);
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emc_set_mem_timings(mode);
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}
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if (perf_modes[old].sys_mult != perf_modes[mode].sys_mult)
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cgu_set_sys_mult(perf_modes[mode].sys_mult);
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if (perf_modes[old].sys_div != perf_modes[mode].sys_div)
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cgu_configure_div(bus_divider, 1, perf_modes[mode].sys_div);
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performance_mode = mode;
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}
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@ -216,12 +178,9 @@ static void pnx0101_init_clocks(void)
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{
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bus_divider = PNX0101_FIRST_DIV_SYS + (CGU.clk_esr[0] >> 1);
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performance_mode = 0;
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emc_set_mem_timings();
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pnx0101_set_performance_mode(2);
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/*
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#ifndef DEBUG
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emc_enable_write_buffers(1);
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#endif
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*/
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cgu_set_sel_stage_input(PNX0101_SEL_STAGE_APB1,
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PNX0101_MAIN_CLOCK_FAST);
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cgu_reset_sel_stage_clocks(PNX0101_FIRST_ESR_APB1, PNX0101_N_ESR_APB1,
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@ -285,7 +244,7 @@ static void undefined_int(void)
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void irq(void)
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{
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int n;
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unsigned long n;
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IRQ_READ(INTVECTOR[0], n)
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(*(interrupt_vector[n >> 3]))();
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}
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@ -323,7 +282,7 @@ void system_init(void)
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IRQ_WRITE_WAIT(INTPRIOMASK[1], 0, v == 0);
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*/
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for (i = 0; i < 0x1c; i++)
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for (i = 1; i <= 0x1c; i++)
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{
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IRQ_WRITE_WAIT(INTREQ[i],
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INTREQ_WEPRIO | INTREQ_WETARGET |
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@ -331,7 +290,7 @@ void system_init(void)
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(v & 0x3010f) == 1);
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IRQ_WRITE_WAIT(INTREQ[i], INTREQ_WEENABLE, (v & 0x10000) == 0);
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IRQ_WRITE_WAIT(INTREQ[i], INTREQ_WEPRIO | 1, (v & 0xf) == 1);
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interrupt_vector[i + 1] = undefined_int;
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interrupt_vector[i] = undefined_int;
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}
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interrupt_vector[0] = undefined_int;
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pnx0101_init_clocks();
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