From 0044a04c22b65b4ac9e9f6e941c2296ce2f7a2e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rg=20Hohensohn?= Date: Fri, 19 Nov 2004 23:04:40 +0000 Subject: [PATCH] the -t test option now does no memory test, but enables 38400 baud on players git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5441 a1c6a512-1295-4272-9138-f99709370657 --- flash/uart_boot/uart_boot.c | 120 +++--------------------------------- 1 file changed, 10 insertions(+), 110 deletions(-) diff --git a/flash/uart_boot/uart_boot.c b/flash/uart_boot/uart_boot.c index 914937305c..f2047d8987 100644 --- a/flash/uart_boot/uart_boot.c +++ b/flash/uart_boot/uart_boot.c @@ -173,7 +173,13 @@ int main(int argc, char* argv[]) if (gCmd.bNoDownload) { // just set our speed - if (!UartConfig(serial_handle, gCmd.bRecorder ? 115200 : 38400, eNOPARITY, eONESTOPBIT, 8)) + int baudrate = gCmd.bRecorder ? 115200 : 14400; + if (!gCmd.bRecorder && gCmd.bTest) + { // experimental Player speedup to 38400 baud + baudrate = 38400; + } + + if (!UartConfig(serial_handle, baudrate, eNOPARITY, eONESTOPBIT, 8)) { printf("Error setting up COM params\n"); exit(1); @@ -198,9 +204,9 @@ int main(int argc, char* argv[]) { // we can be faster SetTargetBaudrate(serial_handle, 11059200, 115200); // set to 115200 } - else - { - SetTargetBaudrate(serial_handle, 12000000, 38400); // set to 38400 + else if (gCmd.bTest) // experimental Player speedup to 38400 baud + { + SetTargetBaudrate(serial_handle, 12000000, 38400); // set to 38400 } } } @@ -345,112 +351,6 @@ int main(int argc, char* argv[]) } - if (gCmd.bTest) // DRAM test - { - static UINT8 abRam[2*1024*1024]; // DRAM copy, not on stack - int i; - int fails; - - // init the DRAM controller like the flash boot does - reg = ReadHalfword(serial_handle, 0x05FFFFCA); // PACR2 - reg &= 0xFFFB; // PA1 config: /RAS - reg |= 0x0008; - WriteHalfword(serial_handle, 0x05FFFFCA, reg); // PACR2 - reg = 0xAFFF; // CS1, CS3 config: /CASH. /CASL - WriteHalfword(serial_handle, 0x05FFFFEE, reg); // CASCR - reg = ReadHalfword(serial_handle, 0x05FFFFA0); // BCR - reg |= 0x8000; // DRAM enable, default bus - WriteHalfword(serial_handle, 0x05FFFFA0, reg); // BCR - reg = ReadHalfword(serial_handle, 0x05FFFFA2); // WCR1 - reg &= 0xFDFD; // 1-cycle CAS - WriteHalfword(serial_handle, 0x05FFFFA2, reg); // WCR1 - reg = 0x0E00; // CAS 35%, multiplexed, 10 bit row addr. - WriteHalfword(serial_handle, 0x05FFFFA8, reg); // DCR - reg = 0x5AB0; // refresh, 4 cycle waitstate - WriteHalfword(serial_handle, 0x05FFFFAC, reg); // RCR - reg = 0x9605; // refresh constant - WriteHalfword(serial_handle, 0x05FFFFB2, reg); // RTCOR - reg = 0xA518; // phi/32 - WriteHalfword(serial_handle, 0x05FFFFAE, reg); // RTCSR - - fails = 0; - memset(abRam, 0xFF, sizeof(abRam)); - printf("writing 0xFF pattern\n"); - WriteByteMultiple(serial_handle, 0x09000000, sizeof(abRam), abRam); - printf("testing marching 0x00\n"); - for (i=0; i